273 lines
12 KiB
Plaintext
273 lines
12 KiB
Plaintext
/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#define GT215 0xa3
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#define GF100 0xc0
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#define GF119 0xd9
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#define GK208 0x108
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#include "os.h"
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// IO addresses
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#define NV_PPWR_INTR_TRIGGER 0x0000
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#define NV_PPWR_INTR_TRIGGER_USER1 0x00000080
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#define NV_PPWR_INTR_TRIGGER_USER0 0x00000040
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#define NV_PPWR_INTR_ACK 0x0004
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#define NV_PPWR_INTR_ACK_SUBINTR 0x00000800
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#define NV_PPWR_INTR_ACK_WATCHDOG 0x00000002
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#define NV_PPWR_INTR 0x0008
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#define NV_PPWR_INTR_SUBINTR 0x00000800
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#define NV_PPWR_INTR_USER1 0x00000080
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#define NV_PPWR_INTR_USER0 0x00000040
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#define NV_PPWR_INTR_PAUSE 0x00000020
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#define NV_PPWR_INTR_WATCHDOG 0x00000002
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#define NV_PPWR_INTR_EN_SET 0x0010
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#define NV_PPWR_INTR_EN_SET_SUBINTR 0x00000800
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#define NV_PPWR_INTR_EN_SET_WATCHDOG 0x00000002
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#define NV_PPWR_INTR_EN_CLR 0x0014
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#define NV_PPWR_INTR_EN_CLR_MASK /* fuck i hate envyas */ -1
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#define NV_PPWR_INTR_ROUTE 0x001c
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#define NV_PPWR_TIMER_LOW 0x002c
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#define NV_PPWR_WATCHDOG_TIME 0x0034
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#define NV_PPWR_WATCHDOG_ENABLE 0x0038
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#define NV_PPWR_CAPS 0x0108
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#define NV_PPWR_UAS_CONFIG 0x0164
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#define NV_PPWR_UAS_CONFIG_ENABLE 0x00010000
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#if NVKM_PPWR_CHIPSET >= GK208
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#define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x0450)
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#endif
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#define NV_PPWR_FIFO_PUT(i) (4 * (i) + 0x04a0)
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#define NV_PPWR_FIFO_GET(i) (4 * (i) + 0x04b0)
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#define NV_PPWR_FIFO_INTR 0x04c0
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#define NV_PPWR_FIFO_INTR_EN 0x04c4
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#define NV_PPWR_RFIFO_PUT 0x04c8
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#define NV_PPWR_RFIFO_GET 0x04cc
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#define NV_PPWR_H2D 0x04d0
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#define NV_PPWR_D2H 0x04dc
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#if NVKM_PPWR_CHIPSET < GK208
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#define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x05d0)
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#endif
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#define NV_PPWR_SUBINTR 0x0688
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#define NV_PPWR_SUBINTR_FIFO 0x00000002
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#define NV_PPWR_MMIO_ADDR 0x07a0
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#define NV_PPWR_MMIO_DATA 0x07a4
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#define NV_PPWR_MMIO_CTRL 0x07ac
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#define NV_PPWR_MMIO_CTRL_TRIGGER 0x00010000
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#define NV_PPWR_MMIO_CTRL_STATUS 0x00007000
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#define NV_PPWR_MMIO_CTRL_STATUS_IDLE 0x00000000
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#define NV_PPWR_MMIO_CTRL_MASK 0x000000f0
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#define NV_PPWR_MMIO_CTRL_MASK_B32_0 0x000000f0
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#define NV_PPWR_MMIO_CTRL_OP 0x00000003
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#define NV_PPWR_MMIO_CTRL_OP_RD 0x00000001
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#define NV_PPWR_MMIO_CTRL_OP_WR 0x00000002
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#define NV_PPWR_OUTPUT 0x07c0
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#define NV_PPWR_OUTPUT_FB_PAUSE 0x00000004
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#if NVKM_PPWR_CHIPSET < GF119
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#define NV_PPWR_OUTPUT_I2C_3_SCL 0x00000100
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#define NV_PPWR_OUTPUT_I2C_3_SDA 0x00000200
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#define NV_PPWR_OUTPUT_I2C_0_SCL 0x00001000
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#define NV_PPWR_OUTPUT_I2C_0_SDA 0x00002000
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#define NV_PPWR_OUTPUT_I2C_1_SCL 0x00004000
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#define NV_PPWR_OUTPUT_I2C_1_SDA 0x00008000
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#define NV_PPWR_OUTPUT_I2C_2_SCL 0x00010000
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#define NV_PPWR_OUTPUT_I2C_2_SDA 0x00020000
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#define NV_PPWR_OUTPUT_I2C_4_SCL 0x00040000
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#define NV_PPWR_OUTPUT_I2C_4_SDA 0x00080000
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#define NV_PPWR_OUTPUT_I2C_5_SCL 0x00100000
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#define NV_PPWR_OUTPUT_I2C_5_SDA 0x00200000
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#define NV_PPWR_OUTPUT_I2C_6_SCL 0x00400000
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#define NV_PPWR_OUTPUT_I2C_6_SDA 0x00800000
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#define NV_PPWR_OUTPUT_I2C_7_SCL 0x01000000
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#define NV_PPWR_OUTPUT_I2C_7_SDA 0x02000000
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#define NV_PPWR_OUTPUT_I2C_8_SCL 0x04000000
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#define NV_PPWR_OUTPUT_I2C_8_SDA 0x08000000
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#define NV_PPWR_OUTPUT_I2C_9_SCL 0x10000000
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#define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000
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#else
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#define NV_PPWR_OUTPUT_I2C_0_SCL 0x00000400
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#define NV_PPWR_OUTPUT_I2C_1_SCL 0x00000800
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#define NV_PPWR_OUTPUT_I2C_2_SCL 0x00001000
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#define NV_PPWR_OUTPUT_I2C_3_SCL 0x00002000
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#define NV_PPWR_OUTPUT_I2C_4_SCL 0x00004000
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#define NV_PPWR_OUTPUT_I2C_5_SCL 0x00008000
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#define NV_PPWR_OUTPUT_I2C_6_SCL 0x00010000
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#define NV_PPWR_OUTPUT_I2C_7_SCL 0x00020000
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#define NV_PPWR_OUTPUT_I2C_8_SCL 0x00040000
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#define NV_PPWR_OUTPUT_I2C_9_SCL 0x00080000
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#define NV_PPWR_OUTPUT_I2C_0_SDA 0x00100000
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#define NV_PPWR_OUTPUT_I2C_1_SDA 0x00200000
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#define NV_PPWR_OUTPUT_I2C_2_SDA 0x00400000
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#define NV_PPWR_OUTPUT_I2C_3_SDA 0x00800000
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#define NV_PPWR_OUTPUT_I2C_4_SDA 0x01000000
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#define NV_PPWR_OUTPUT_I2C_5_SDA 0x02000000
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#define NV_PPWR_OUTPUT_I2C_6_SDA 0x04000000
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#define NV_PPWR_OUTPUT_I2C_7_SDA 0x08000000
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#define NV_PPWR_OUTPUT_I2C_8_SDA 0x10000000
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#define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000
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#endif
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#define NV_PPWR_INPUT 0x07c4
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#define NV_PPWR_OUTPUT_SET 0x07e0
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#define NV_PPWR_OUTPUT_SET_FB_PAUSE 0x00000004
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#define NV_PPWR_OUTPUT_CLR 0x07e4
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#define NV_PPWR_OUTPUT_CLR_FB_PAUSE 0x00000004
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// Inter-process message format
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.equ #msg_process 0x00 /* send() target, recv() sender */
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.equ #msg_message 0x04
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.equ #msg_data0 0x08
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.equ #msg_data1 0x0c
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// Kernel message IDs
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#define KMSG_FIFO 0x00000000
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#define KMSG_ALARM 0x00000001
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// Process message queue description
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.equ #proc_qlen 4 // log2(size of queue entry in bytes)
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.equ #proc_qnum 2 // log2(max number of entries in queue)
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.equ #proc_qmaskb (1 << #proc_qnum) // max number of entries in queue
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.equ #proc_qmaskp (#proc_qmaskb - 1)
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.equ #proc_qmaskf ((#proc_qmaskb << 1) - 1)
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.equ #proc_qsize (1 << (#proc_qlen + #proc_qnum))
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// Process table entry
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.equ #proc_id 0x00
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.equ #proc_init 0x04
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.equ #proc_recv 0x08
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.equ #proc_time 0x0c
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.equ #proc_qput 0x10
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.equ #proc_qget 0x14
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.equ #proc_queue 0x18
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.equ #proc_size (0x18 + #proc_qsize)
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#define process(id,init,recv) /*
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*/ .b32 id /*
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*/ .b32 init /*
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*/ .b32 recv /*
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*/ .b32 0 /*
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*/ .b32 0 /*
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*/ .b32 0 /*
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*/ .skip 64
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#if NVKM_PPWR_CHIPSET < GK208
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#define imm32(reg,val) /*
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*/ movw reg ((val) & 0x0000ffff) /*
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*/ sethi reg ((val) & 0xffff0000)
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#else
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#define imm32(reg,val) /*
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*/ mov reg (val)
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#endif
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#ifndef NVKM_FALCON_UNSHIFTED_IO
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#define nv_iord(reg,ior) /*
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*/ mov reg ior /*
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*/ shl b32 reg 6 /*
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*/ iord reg I[reg + 0x000]
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#else
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#define nv_iord(reg,ior) /*
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*/ mov reg ior /*
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*/ iord reg I[reg + 0x000]
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#endif
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#ifndef NVKM_FALCON_UNSHIFTED_IO
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#define nv_iowr(ior,reg) /*
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*/ mov $r0 ior /*
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*/ shl b32 $r0 6 /*
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*/ iowr I[$r0 + 0x000] reg /*
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*/ clear b32 $r0
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#else
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#define nv_iowr(ior,reg) /*
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*/ mov $r0 ior /*
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*/ iowr I[$r0 + 0x000] reg /*
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*/ clear b32 $r0
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#endif
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#ifndef NVKM_FALCON_UNSHIFTED_IO
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#define nv_iowrs(ior,reg) /*
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*/ mov $r0 ior /*
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*/ shl b32 $r0 6 /*
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*/ iowrs I[$r0 + 0x000] reg /*
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*/ clear b32 $r0
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#else
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#define nv_iowrs(ior,reg) /*
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*/ mov $r0 ior /*
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*/ iowrs I[$r0 + 0x000] reg /*
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*/ clear b32 $r0
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#endif
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#define hash #
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#define fn(a) a
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#ifndef NVKM_FALCON_PC24
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#define call(a) call fn(hash)a
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#else
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#define call(a) lcall fn(hash)a
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#endif
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#ifndef NVKM_FALCON_MMIO_UAS
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#define nv_rd32(reg,addr) /*
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*/ mov b32 $r14 addr /*
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*/ call(rd32) /*
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*/ mov b32 reg $r13
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#else
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#define nv_rd32(reg,addr) /*
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*/ sethi $r0 0x14000000 /*
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*/ or $r0 addr /*
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*/ ld b32 reg D[$r0] /*
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*/ clear b32 $r0
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#endif
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#if !defined(NVKM_FALCON_MMIO_UAS) || defined(NVKM_FALCON_MMIO_TRAP)
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#define nv_wr32(addr,reg) /*
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*/ push addr /*
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*/ push reg /*
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*/ pop $r13 /*
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*/ pop $r14 /*
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*/ call(wr32)
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#else
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#define nv_wr32(addr,reg) /*
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*/ sethi $r0 0x14000000 /*
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*/ or $r0 addr /*
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*/ st b32 D[$r0] reg /*
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*/ clear b32 $r0
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#endif
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#define st(size, addr, reg) /*
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*/ imm32($r0, addr) /*
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*/ st size D[$r0] reg /*
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*/ clear b32 $r0
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#define ld(size, reg, addr) /*
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*/ imm32($r0, addr) /*
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*/ ld size reg D[$r0] /*
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*/ clear b32 $r0
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// does a 64+64 -> 64 unsigned addition (C = A + B)
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#define addu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /*
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*/ add b32 reg_a_c_lo b_lo /*
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*/ adc b32 reg_a_c_hi b_hi
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// does a 64+64 -> 64 substraction (C = A - B)
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#define subu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /*
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*/ sub b32 reg_a_c_lo b_lo /*
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*/ sbb b32 reg_a_c_hi b_hi
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