817 lines
20 KiB
C
817 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G2L MIPI DSI Encoder Driver
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*
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* Copyright (C) 2022 Renesas Electronics Corporation
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_of.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_probe_helper.h>
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#include "rzg2l_mipi_dsi_regs.h"
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struct rzg2l_mipi_dsi {
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struct device *dev;
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void __iomem *mmio;
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struct reset_control *rstc;
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struct reset_control *arstc;
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struct reset_control *prstc;
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struct mipi_dsi_host host;
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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struct clk *vclk;
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enum mipi_dsi_pixel_format format;
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unsigned int num_data_lanes;
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unsigned int lanes;
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unsigned long mode_flags;
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};
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static inline struct rzg2l_mipi_dsi *
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bridge_to_rzg2l_mipi_dsi(struct drm_bridge *bridge)
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{
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return container_of(bridge, struct rzg2l_mipi_dsi, bridge);
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}
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static inline struct rzg2l_mipi_dsi *
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host_to_rzg2l_mipi_dsi(struct mipi_dsi_host *host)
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{
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return container_of(host, struct rzg2l_mipi_dsi, host);
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}
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struct rzg2l_mipi_dsi_timings {
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unsigned long hsfreq_max;
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u32 t_init;
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u32 tclk_prepare;
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u32 ths_prepare;
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u32 tclk_zero;
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u32 tclk_pre;
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u32 tclk_post;
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u32 tclk_trail;
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u32 ths_zero;
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u32 ths_trail;
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u32 ths_exit;
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u32 tlpx;
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};
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static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = {
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{
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.hsfreq_max = 80000,
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.t_init = 79801,
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.tclk_prepare = 8,
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.ths_prepare = 13,
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.tclk_zero = 33,
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.tclk_pre = 24,
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.tclk_post = 94,
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.tclk_trail = 10,
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.ths_zero = 23,
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.ths_trail = 17,
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.ths_exit = 13,
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.tlpx = 6,
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},
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{
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.hsfreq_max = 125000,
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.t_init = 79801,
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.tclk_prepare = 8,
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.ths_prepare = 12,
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.tclk_zero = 33,
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.tclk_pre = 15,
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.tclk_post = 94,
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.tclk_trail = 10,
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.ths_zero = 23,
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.ths_trail = 17,
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.ths_exit = 13,
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.tlpx = 6,
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},
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{
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.hsfreq_max = 250000,
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.t_init = 79801,
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.tclk_prepare = 8,
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.ths_prepare = 12,
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.tclk_zero = 33,
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.tclk_pre = 13,
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.tclk_post = 94,
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.tclk_trail = 10,
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.ths_zero = 23,
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.ths_trail = 16,
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.ths_exit = 13,
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.tlpx = 6,
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},
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{
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.hsfreq_max = 360000,
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.t_init = 79801,
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.tclk_prepare = 8,
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.ths_prepare = 10,
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.tclk_zero = 33,
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.tclk_pre = 4,
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.tclk_post = 35,
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.tclk_trail = 7,
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.ths_zero = 16,
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.ths_trail = 9,
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.ths_exit = 13,
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.tlpx = 6,
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},
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{
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.hsfreq_max = 720000,
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.t_init = 79801,
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.tclk_prepare = 8,
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.ths_prepare = 9,
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.tclk_zero = 33,
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.tclk_pre = 4,
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.tclk_post = 35,
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.tclk_trail = 7,
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.ths_zero = 16,
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.ths_trail = 9,
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.ths_exit = 13,
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.tlpx = 6,
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},
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{
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.hsfreq_max = 1500000,
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.t_init = 79801,
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.tclk_prepare = 8,
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.ths_prepare = 9,
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.tclk_zero = 33,
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.tclk_pre = 4,
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.tclk_post = 35,
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.tclk_trail = 7,
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.ths_zero = 16,
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.ths_trail = 9,
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.ths_exit = 13,
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.tlpx = 6,
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},
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};
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static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)
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{
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iowrite32(data, dsi->mmio + reg);
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}
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static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)
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{
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iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg);
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}
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static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
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{
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return ioread32(dsi->mmio + reg);
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}
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static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
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{
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return ioread32(dsi->mmio + LINK_REG_OFFSET + reg);
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}
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/* -----------------------------------------------------------------------------
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* Hardware Setup
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*/
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static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
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unsigned long hsfreq)
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{
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const struct rzg2l_mipi_dsi_timings *dphy_timings;
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unsigned int i;
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u32 dphyctrl0;
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u32 dphytim0;
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u32 dphytim1;
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u32 dphytim2;
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u32 dphytim3;
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int ret;
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/* All DSI global operation timings are set with recommended setting */
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for (i = 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) {
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dphy_timings = &rzg2l_mipi_dsi_global_timings[i];
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if (hsfreq <= dphy_timings->hsfreq_max)
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break;
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}
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/* Initializing DPHY before accessing LINK */
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dphyctrl0 = DSIDPHYCTRL0_CAL_EN_HSRX_OFS | DSIDPHYCTRL0_CMN_MASTER_EN |
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DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR;
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rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
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usleep_range(20, 30);
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dphyctrl0 |= DSIDPHYCTRL0_EN_LDO1200;
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rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
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usleep_range(10, 20);
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dphytim0 = DSIDPHYTIM0_TCLK_MISS(0) |
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DSIDPHYTIM0_T_INIT(dphy_timings->t_init);
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dphytim1 = DSIDPHYTIM1_THS_PREPARE(dphy_timings->ths_prepare) |
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DSIDPHYTIM1_TCLK_PREPARE(dphy_timings->tclk_prepare) |
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DSIDPHYTIM1_THS_SETTLE(0) |
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DSIDPHYTIM1_TCLK_SETTLE(0);
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dphytim2 = DSIDPHYTIM2_TCLK_TRAIL(dphy_timings->tclk_trail) |
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DSIDPHYTIM2_TCLK_POST(dphy_timings->tclk_post) |
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DSIDPHYTIM2_TCLK_PRE(dphy_timings->tclk_pre) |
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DSIDPHYTIM2_TCLK_ZERO(dphy_timings->tclk_zero);
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dphytim3 = DSIDPHYTIM3_TLPX(dphy_timings->tlpx) |
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DSIDPHYTIM3_THS_EXIT(dphy_timings->ths_exit) |
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DSIDPHYTIM3_THS_TRAIL(dphy_timings->ths_trail) |
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DSIDPHYTIM3_THS_ZERO(dphy_timings->ths_zero);
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rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM0, dphytim0);
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rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM1, dphytim1);
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rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM2, dphytim2);
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rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM3, dphytim3);
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ret = reset_control_deassert(dsi->rstc);
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if (ret < 0)
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return ret;
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udelay(1);
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return 0;
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}
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static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi)
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{
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u32 dphyctrl0;
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dphyctrl0 = rzg2l_mipi_dsi_phy_read(dsi, DSIDPHYCTRL0);
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dphyctrl0 &= ~(DSIDPHYCTRL0_EN_LDO1200 | DSIDPHYCTRL0_EN_BGR);
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rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
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reset_control_assert(dsi->rstc);
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}
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static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
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const struct drm_display_mode *mode)
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{
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unsigned long hsfreq;
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unsigned int bpp;
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u32 txsetr;
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u32 clstptsetr;
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u32 lptrnstsetr;
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u32 clkkpt;
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u32 clkbfht;
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u32 clkstpt;
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u32 golpbkt;
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int ret;
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/*
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* Relationship between hsclk and vclk must follow
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* vclk * bpp = hsclk * 8 * lanes
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* where vclk: video clock (Hz)
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* bpp: video pixel bit depth
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* hsclk: DSI HS Byte clock frequency (Hz)
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* lanes: number of data lanes
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*
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* hsclk(bit) = hsclk(byte) * 8
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*/
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bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
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hsfreq = (mode->clock * bpp * 8) / (8 * dsi->lanes);
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ret = pm_runtime_resume_and_get(dsi->dev);
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if (ret < 0)
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return ret;
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clk_set_rate(dsi->vclk, mode->clock * 1000);
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ret = rzg2l_mipi_dsi_dphy_init(dsi, hsfreq);
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if (ret < 0)
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goto err_phy;
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/* Enable Data lanes and Clock lanes */
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txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;
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rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr);
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/*
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* Global timings characteristic depends on high speed Clock Frequency
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* Currently MIPI DSI-IF just supports maximum FHD@60 with:
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* - videoclock = 148.5 (MHz)
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* - bpp: maximum 24bpp
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* - data lanes: maximum 4 lanes
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* Therefore maximum hsclk will be 891 Mbps.
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*/
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if (hsfreq > 445500) {
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clkkpt = 12;
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clkbfht = 15;
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clkstpt = 48;
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golpbkt = 75;
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} else if (hsfreq > 250000) {
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clkkpt = 7;
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clkbfht = 8;
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clkstpt = 27;
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golpbkt = 40;
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} else {
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clkkpt = 8;
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clkbfht = 6;
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clkstpt = 24;
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golpbkt = 29;
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}
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clstptsetr = CLSTPTSETR_CLKKPT(clkkpt) | CLSTPTSETR_CLKBFHT(clkbfht) |
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CLSTPTSETR_CLKSTPT(clkstpt);
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rzg2l_mipi_dsi_link_write(dsi, CLSTPTSETR, clstptsetr);
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lptrnstsetr = LPTRNSTSETR_GOLPBKT(golpbkt);
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rzg2l_mipi_dsi_link_write(dsi, LPTRNSTSETR, lptrnstsetr);
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return 0;
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err_phy:
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rzg2l_mipi_dsi_dphy_exit(dsi);
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pm_runtime_put(dsi->dev);
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return ret;
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}
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static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi)
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{
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rzg2l_mipi_dsi_dphy_exit(dsi);
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pm_runtime_put(dsi->dev);
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}
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static void rzg2l_mipi_dsi_set_display_timing(struct rzg2l_mipi_dsi *dsi,
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const struct drm_display_mode *mode)
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{
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u32 vich1ppsetr;
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u32 vich1vssetr;
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u32 vich1vpsetr;
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u32 vich1hssetr;
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u32 vich1hpsetr;
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int dsi_format;
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u32 delay[2];
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u8 index;
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/* Configuration for Pixel Packet */
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dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
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switch (dsi_format) {
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case 24:
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vich1ppsetr = VICH1PPSETR_DT_RGB24;
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break;
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case 18:
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vich1ppsetr = VICH1PPSETR_DT_RGB18;
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break;
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}
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if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) &&
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!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST))
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vich1ppsetr |= VICH1PPSETR_TXESYNC_PULSE;
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rzg2l_mipi_dsi_link_write(dsi, VICH1PPSETR, vich1ppsetr);
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/* Configuration for Video Parameters */
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vich1vssetr = VICH1VSSETR_VACTIVE(mode->vdisplay) |
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VICH1VSSETR_VSA(mode->vsync_end - mode->vsync_start);
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vich1vssetr |= (mode->flags & DRM_MODE_FLAG_PVSYNC) ?
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VICH1VSSETR_VSPOL_HIGH : VICH1VSSETR_VSPOL_LOW;
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vich1vpsetr = VICH1VPSETR_VFP(mode->vsync_start - mode->vdisplay) |
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VICH1VPSETR_VBP(mode->vtotal - mode->vsync_end);
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vich1hssetr = VICH1HSSETR_HACTIVE(mode->hdisplay) |
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VICH1HSSETR_HSA(mode->hsync_end - mode->hsync_start);
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vich1hssetr |= (mode->flags & DRM_MODE_FLAG_PHSYNC) ?
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VICH1HSSETR_HSPOL_HIGH : VICH1HSSETR_HSPOL_LOW;
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vich1hpsetr = VICH1HPSETR_HFP(mode->hsync_start - mode->hdisplay) |
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VICH1HPSETR_HBP(mode->htotal - mode->hsync_end);
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rzg2l_mipi_dsi_link_write(dsi, VICH1VSSETR, vich1vssetr);
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rzg2l_mipi_dsi_link_write(dsi, VICH1VPSETR, vich1vpsetr);
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rzg2l_mipi_dsi_link_write(dsi, VICH1HSSETR, vich1hssetr);
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rzg2l_mipi_dsi_link_write(dsi, VICH1HPSETR, vich1hpsetr);
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/*
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* Configuration for Delay Value
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* Delay value based on 2 ranges of video clock.
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* 74.25MHz is videoclock of HD@60p or FHD@30p
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*/
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if (mode->clock > 74250) {
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delay[0] = 231;
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delay[1] = 216;
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} else {
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delay[0] = 220;
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delay[1] = 212;
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}
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if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
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index = 0;
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else
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index = 1;
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rzg2l_mipi_dsi_link_write(dsi, VICH1SET1R,
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VICH1SET1R_DLY(delay[index]));
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}
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static int rzg2l_mipi_dsi_start_hs_clock(struct rzg2l_mipi_dsi *dsi)
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{
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bool is_clk_cont;
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u32 hsclksetr;
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u32 status;
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int ret;
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is_clk_cont = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS);
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/* Start HS clock */
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hsclksetr = HSCLKSETR_HSCLKRUN_HS | (is_clk_cont ?
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HSCLKSETR_HSCLKMODE_CONT :
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HSCLKSETR_HSCLKMODE_NON_CONT);
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rzg2l_mipi_dsi_link_write(dsi, HSCLKSETR, hsclksetr);
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if (is_clk_cont) {
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ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
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status & PLSR_CLLP2HS,
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2000, 20000, false, dsi, PLSR);
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if (ret < 0) {
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dev_err(dsi->dev, "failed to start HS clock\n");
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return ret;
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}
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}
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dev_dbg(dsi->dev, "Start High Speed Clock with %s clock mode",
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is_clk_cont ? "continuous" : "non-continuous");
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return 0;
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}
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static int rzg2l_mipi_dsi_stop_hs_clock(struct rzg2l_mipi_dsi *dsi)
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{
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bool is_clk_cont;
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u32 status;
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int ret;
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is_clk_cont = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS);
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/* Stop HS clock */
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rzg2l_mipi_dsi_link_write(dsi, HSCLKSETR,
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is_clk_cont ? HSCLKSETR_HSCLKMODE_CONT :
|
|
HSCLKSETR_HSCLKMODE_NON_CONT);
|
|
|
|
if (is_clk_cont) {
|
|
ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
|
|
status & PLSR_CLHS2LP,
|
|
2000, 20000, false, dsi, PLSR);
|
|
if (ret < 0) {
|
|
dev_err(dsi->dev, "failed to stop HS clock\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rzg2l_mipi_dsi_start_video(struct rzg2l_mipi_dsi *dsi)
|
|
{
|
|
u32 vich1set0r;
|
|
u32 status;
|
|
int ret;
|
|
|
|
/* Configuration for Blanking sequence and start video input*/
|
|
vich1set0r = VICH1SET0R_HFPNOLP | VICH1SET0R_HBPNOLP |
|
|
VICH1SET0R_HSANOLP | VICH1SET0R_VSTART;
|
|
rzg2l_mipi_dsi_link_write(dsi, VICH1SET0R, vich1set0r);
|
|
|
|
ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
|
|
status & VICH1SR_VIRDY,
|
|
2000, 20000, false, dsi, VICH1SR);
|
|
if (ret < 0)
|
|
dev_err(dsi->dev, "Failed to start video signal input\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rzg2l_mipi_dsi_stop_video(struct rzg2l_mipi_dsi *dsi)
|
|
{
|
|
u32 status;
|
|
int ret;
|
|
|
|
rzg2l_mipi_dsi_link_write(dsi, VICH1SET0R, VICH1SET0R_VSTPAFT);
|
|
ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
|
|
(status & VICH1SR_STOP) && (!(status & VICH1SR_RUNNING)),
|
|
2000, 20000, false, dsi, VICH1SR);
|
|
if (ret < 0)
|
|
goto err;
|
|
|
|
ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
|
|
!(status & LINKSR_HSBUSY),
|
|
2000, 20000, false, dsi, LINKSR);
|
|
if (ret < 0)
|
|
goto err;
|
|
|
|
return 0;
|
|
|
|
err:
|
|
dev_err(dsi->dev, "Failed to stop video signal input\n");
|
|
return ret;
|
|
}
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Bridge
|
|
*/
|
|
|
|
static int rzg2l_mipi_dsi_attach(struct drm_bridge *bridge,
|
|
enum drm_bridge_attach_flags flags)
|
|
{
|
|
struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
|
|
|
|
return drm_bridge_attach(bridge->encoder, dsi->next_bridge, bridge,
|
|
flags);
|
|
}
|
|
|
|
static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
|
|
struct drm_bridge_state *old_bridge_state)
|
|
{
|
|
struct drm_atomic_state *state = old_bridge_state->base.state;
|
|
struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
|
|
const struct drm_display_mode *mode;
|
|
struct drm_connector *connector;
|
|
struct drm_crtc *crtc;
|
|
int ret;
|
|
|
|
connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
|
|
crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
|
|
mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
|
|
|
|
ret = rzg2l_mipi_dsi_startup(dsi, mode);
|
|
if (ret < 0)
|
|
return;
|
|
|
|
rzg2l_mipi_dsi_set_display_timing(dsi, mode);
|
|
|
|
ret = rzg2l_mipi_dsi_start_hs_clock(dsi);
|
|
if (ret < 0)
|
|
goto err_stop;
|
|
|
|
ret = rzg2l_mipi_dsi_start_video(dsi);
|
|
if (ret < 0)
|
|
goto err_stop_clock;
|
|
|
|
return;
|
|
|
|
err_stop_clock:
|
|
rzg2l_mipi_dsi_stop_hs_clock(dsi);
|
|
err_stop:
|
|
rzg2l_mipi_dsi_stop(dsi);
|
|
}
|
|
|
|
static void rzg2l_mipi_dsi_atomic_disable(struct drm_bridge *bridge,
|
|
struct drm_bridge_state *old_bridge_state)
|
|
{
|
|
struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
|
|
|
|
rzg2l_mipi_dsi_stop_video(dsi);
|
|
rzg2l_mipi_dsi_stop_hs_clock(dsi);
|
|
rzg2l_mipi_dsi_stop(dsi);
|
|
}
|
|
|
|
static enum drm_mode_status
|
|
rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
|
|
const struct drm_display_info *info,
|
|
const struct drm_display_mode *mode)
|
|
{
|
|
if (mode->clock > 148500)
|
|
return MODE_CLOCK_HIGH;
|
|
|
|
return MODE_OK;
|
|
}
|
|
|
|
static const struct drm_bridge_funcs rzg2l_mipi_dsi_bridge_ops = {
|
|
.attach = rzg2l_mipi_dsi_attach,
|
|
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
|
|
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
|
|
.atomic_reset = drm_atomic_helper_bridge_reset,
|
|
.atomic_enable = rzg2l_mipi_dsi_atomic_enable,
|
|
.atomic_disable = rzg2l_mipi_dsi_atomic_disable,
|
|
.mode_valid = rzg2l_mipi_dsi_bridge_mode_valid,
|
|
};
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Host setting
|
|
*/
|
|
|
|
static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host,
|
|
struct mipi_dsi_device *device)
|
|
{
|
|
struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
|
|
int ret;
|
|
|
|
if (device->lanes > dsi->num_data_lanes) {
|
|
dev_err(dsi->dev,
|
|
"Number of lines of device (%u) exceeds host (%u)\n",
|
|
device->lanes, dsi->num_data_lanes);
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (mipi_dsi_pixel_format_to_bpp(device->format)) {
|
|
case 24:
|
|
case 18:
|
|
break;
|
|
default:
|
|
dev_err(dsi->dev, "Unsupported format 0x%04x\n", device->format);
|
|
return -EINVAL;
|
|
}
|
|
|
|
dsi->lanes = device->lanes;
|
|
dsi->format = device->format;
|
|
dsi->mode_flags = device->mode_flags;
|
|
|
|
dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
|
|
1, 0);
|
|
if (IS_ERR(dsi->next_bridge)) {
|
|
ret = PTR_ERR(dsi->next_bridge);
|
|
dev_err(dsi->dev, "failed to get next bridge: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
drm_bridge_add(&dsi->bridge);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rzg2l_mipi_dsi_host_detach(struct mipi_dsi_host *host,
|
|
struct mipi_dsi_device *device)
|
|
{
|
|
struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
|
|
|
|
drm_bridge_remove(&dsi->bridge);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct mipi_dsi_host_ops rzg2l_mipi_dsi_host_ops = {
|
|
.attach = rzg2l_mipi_dsi_host_attach,
|
|
.detach = rzg2l_mipi_dsi_host_detach,
|
|
};
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Power Management
|
|
*/
|
|
|
|
static int __maybe_unused rzg2l_mipi_pm_runtime_suspend(struct device *dev)
|
|
{
|
|
struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev);
|
|
|
|
reset_control_assert(dsi->prstc);
|
|
reset_control_assert(dsi->arstc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused rzg2l_mipi_pm_runtime_resume(struct device *dev)
|
|
{
|
|
struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = reset_control_deassert(dsi->arstc);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = reset_control_deassert(dsi->prstc);
|
|
if (ret < 0)
|
|
reset_control_assert(dsi->arstc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops rzg2l_mipi_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(rzg2l_mipi_pm_runtime_suspend, rzg2l_mipi_pm_runtime_resume, NULL)
|
|
};
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Probe & Remove
|
|
*/
|
|
|
|
static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
|
|
{
|
|
unsigned int num_data_lanes;
|
|
struct rzg2l_mipi_dsi *dsi;
|
|
u32 txsetr;
|
|
int ret;
|
|
|
|
dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
|
|
if (!dsi)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, dsi);
|
|
dsi->dev = &pdev->dev;
|
|
|
|
ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
|
|
if (ret < 0)
|
|
return dev_err_probe(dsi->dev, ret,
|
|
"missing or invalid data-lanes property\n");
|
|
|
|
num_data_lanes = ret;
|
|
|
|
dsi->mmio = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(dsi->mmio))
|
|
return PTR_ERR(dsi->mmio);
|
|
|
|
dsi->vclk = devm_clk_get(dsi->dev, "vclk");
|
|
if (IS_ERR(dsi->vclk))
|
|
return PTR_ERR(dsi->vclk);
|
|
|
|
dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
|
|
if (IS_ERR(dsi->rstc))
|
|
return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
|
|
"failed to get rst\n");
|
|
|
|
dsi->arstc = devm_reset_control_get_exclusive(dsi->dev, "arst");
|
|
if (IS_ERR(dsi->arstc))
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(dsi->arstc),
|
|
"failed to get arst\n");
|
|
|
|
dsi->prstc = devm_reset_control_get_exclusive(dsi->dev, "prst");
|
|
if (IS_ERR(dsi->prstc))
|
|
return dev_err_probe(dsi->dev, PTR_ERR(dsi->prstc),
|
|
"failed to get prst\n");
|
|
|
|
platform_set_drvdata(pdev, dsi);
|
|
|
|
pm_runtime_enable(dsi->dev);
|
|
|
|
ret = pm_runtime_resume_and_get(dsi->dev);
|
|
if (ret < 0)
|
|
goto err_pm_disable;
|
|
|
|
/*
|
|
* TXSETR register can be read only after DPHY init. But during probe
|
|
* mode->clock and format are not available. So initialize DPHY with
|
|
* timing parameters for 80Mbps.
|
|
*/
|
|
ret = rzg2l_mipi_dsi_dphy_init(dsi, 80000);
|
|
if (ret < 0)
|
|
goto err_phy;
|
|
|
|
txsetr = rzg2l_mipi_dsi_link_read(dsi, TXSETR);
|
|
dsi->num_data_lanes = min(((txsetr >> 16) & 3) + 1, num_data_lanes);
|
|
rzg2l_mipi_dsi_dphy_exit(dsi);
|
|
pm_runtime_put(dsi->dev);
|
|
|
|
/* Initialize the DRM bridge. */
|
|
dsi->bridge.funcs = &rzg2l_mipi_dsi_bridge_ops;
|
|
dsi->bridge.of_node = dsi->dev->of_node;
|
|
|
|
/* Init host device */
|
|
dsi->host.dev = dsi->dev;
|
|
dsi->host.ops = &rzg2l_mipi_dsi_host_ops;
|
|
ret = mipi_dsi_host_register(&dsi->host);
|
|
if (ret < 0)
|
|
goto err_pm_disable;
|
|
|
|
return 0;
|
|
|
|
err_phy:
|
|
rzg2l_mipi_dsi_dphy_exit(dsi);
|
|
pm_runtime_put(dsi->dev);
|
|
err_pm_disable:
|
|
pm_runtime_disable(dsi->dev);
|
|
return ret;
|
|
}
|
|
|
|
static int rzg2l_mipi_dsi_remove(struct platform_device *pdev)
|
|
{
|
|
struct rzg2l_mipi_dsi *dsi = platform_get_drvdata(pdev);
|
|
|
|
mipi_dsi_host_unregister(&dsi->host);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id rzg2l_mipi_dsi_of_table[] = {
|
|
{ .compatible = "renesas,rzg2l-mipi-dsi" },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, rzg2l_mipi_dsi_of_table);
|
|
|
|
static struct platform_driver rzg2l_mipi_dsi_platform_driver = {
|
|
.probe = rzg2l_mipi_dsi_probe,
|
|
.remove = rzg2l_mipi_dsi_remove,
|
|
.driver = {
|
|
.name = "rzg2l-mipi-dsi",
|
|
.pm = &rzg2l_mipi_pm_ops,
|
|
.of_match_table = rzg2l_mipi_dsi_of_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(rzg2l_mipi_dsi_platform_driver);
|
|
|
|
MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
|
|
MODULE_DESCRIPTION("Renesas RZ/G2L MIPI DSI Encoder Driver");
|
|
MODULE_LICENSE("GPL");
|