431 lines
9.9 KiB
C
431 lines
9.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author:Mark Yao <mark.yao@rock-chips.com>
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*/
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#ifndef _ROCKCHIP_DRM_VOP_H
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#define _ROCKCHIP_DRM_VOP_H
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/*
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* major: IP major version, used for IP structure
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* minor: big feature change under same structure
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*/
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#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
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#define VOP_MAJOR(version) ((version) >> 8)
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#define VOP_MINOR(version) ((version) & 0xff)
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#define NUM_YUV2YUV_COEFFICIENTS 12
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/* AFBC supports a number of configurable modes. Relevant to us is block size
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* (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like
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* colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode
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* could be enabled via the hreg_block_split register, but is not currently
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* handled. The colourspace transform is implicitly always assumed by the
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* decoder, so consumers must use this transform as well.
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*
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* Failure to match modifiers will cause errors displaying AFBC buffers
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* produced by conformant AFBC producers, including Mesa.
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*/
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#define ROCKCHIP_AFBC_MOD \
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DRM_FORMAT_MOD_ARM_AFBC( \
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AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE \
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| AFBC_FORMAT_MOD_YTR \
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)
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enum vop_data_format {
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VOP_FMT_ARGB8888 = 0,
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VOP_FMT_RGB888,
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VOP_FMT_RGB565,
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VOP_FMT_YUV420SP = 4,
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VOP_FMT_YUV422SP,
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VOP_FMT_YUV444SP,
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};
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struct vop_reg {
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uint32_t mask;
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uint16_t offset;
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uint8_t shift;
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bool write_mask;
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bool relaxed;
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};
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struct vop_afbc {
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struct vop_reg enable;
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struct vop_reg win_sel;
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struct vop_reg format;
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struct vop_reg rb_swap;
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struct vop_reg uv_swap;
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struct vop_reg auto_gating_en;
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struct vop_reg block_split_en;
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struct vop_reg pic_vir_width;
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struct vop_reg tile_num;
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struct vop_reg hreg_block_split;
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struct vop_reg pic_offset;
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struct vop_reg pic_size;
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struct vop_reg dsp_offset;
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struct vop_reg transform_offset;
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struct vop_reg hdr_ptr;
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struct vop_reg half_block_en;
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struct vop_reg xmirror;
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struct vop_reg ymirror;
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struct vop_reg rotate_270;
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struct vop_reg rotate_90;
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struct vop_reg rstn;
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};
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struct vop_modeset {
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struct vop_reg htotal_pw;
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struct vop_reg hact_st_end;
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struct vop_reg hpost_st_end;
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struct vop_reg vtotal_pw;
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struct vop_reg vact_st_end;
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struct vop_reg vpost_st_end;
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};
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struct vop_output {
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struct vop_reg pin_pol;
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struct vop_reg dp_pin_pol;
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struct vop_reg dp_dclk_pol;
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struct vop_reg edp_pin_pol;
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struct vop_reg edp_dclk_pol;
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struct vop_reg hdmi_pin_pol;
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struct vop_reg hdmi_dclk_pol;
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struct vop_reg mipi_pin_pol;
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struct vop_reg mipi_dclk_pol;
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struct vop_reg rgb_pin_pol;
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struct vop_reg rgb_dclk_pol;
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struct vop_reg dp_en;
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struct vop_reg edp_en;
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struct vop_reg hdmi_en;
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struct vop_reg mipi_en;
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struct vop_reg mipi_dual_channel_en;
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struct vop_reg rgb_en;
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};
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struct vop_common {
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struct vop_reg cfg_done;
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struct vop_reg dsp_blank;
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struct vop_reg data_blank;
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struct vop_reg pre_dither_down;
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struct vop_reg dither_down_sel;
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struct vop_reg dither_down_mode;
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struct vop_reg dither_down_en;
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struct vop_reg dither_up;
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struct vop_reg dsp_lut_en;
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struct vop_reg update_gamma_lut;
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struct vop_reg lut_buffer_index;
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struct vop_reg gate_en;
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struct vop_reg mmu_en;
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struct vop_reg out_mode;
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struct vop_reg standby;
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};
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struct vop_misc {
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struct vop_reg global_regdone_en;
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};
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struct vop_intr {
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const int *intrs;
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uint32_t nintrs;
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struct vop_reg line_flag_num[2];
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struct vop_reg enable;
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struct vop_reg clear;
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struct vop_reg status;
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};
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struct vop_scl_extension {
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struct vop_reg cbcr_vsd_mode;
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struct vop_reg cbcr_vsu_mode;
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struct vop_reg cbcr_hsd_mode;
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struct vop_reg cbcr_ver_scl_mode;
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struct vop_reg cbcr_hor_scl_mode;
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struct vop_reg yrgb_vsd_mode;
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struct vop_reg yrgb_vsu_mode;
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struct vop_reg yrgb_hsd_mode;
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struct vop_reg yrgb_ver_scl_mode;
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struct vop_reg yrgb_hor_scl_mode;
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struct vop_reg line_load_mode;
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struct vop_reg cbcr_axi_gather_num;
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struct vop_reg yrgb_axi_gather_num;
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struct vop_reg vsd_cbcr_gt2;
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struct vop_reg vsd_cbcr_gt4;
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struct vop_reg vsd_yrgb_gt2;
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struct vop_reg vsd_yrgb_gt4;
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struct vop_reg bic_coe_sel;
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struct vop_reg cbcr_axi_gather_en;
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struct vop_reg yrgb_axi_gather_en;
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struct vop_reg lb_mode;
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};
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struct vop_scl_regs {
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const struct vop_scl_extension *ext;
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struct vop_reg scale_yrgb_x;
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struct vop_reg scale_yrgb_y;
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struct vop_reg scale_cbcr_x;
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struct vop_reg scale_cbcr_y;
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};
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struct vop_yuv2yuv_phy {
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struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS];
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};
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struct vop_win_phy {
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const struct vop_scl_regs *scl;
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const uint32_t *data_formats;
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uint32_t nformats;
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const uint64_t *format_modifiers;
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struct vop_reg enable;
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struct vop_reg gate;
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struct vop_reg format;
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struct vop_reg rb_swap;
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struct vop_reg uv_swap;
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struct vop_reg act_info;
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struct vop_reg dsp_info;
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struct vop_reg dsp_st;
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struct vop_reg yrgb_mst;
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struct vop_reg uv_mst;
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struct vop_reg yrgb_vir;
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struct vop_reg uv_vir;
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struct vop_reg y_mir_en;
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struct vop_reg x_mir_en;
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struct vop_reg dst_alpha_ctl;
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struct vop_reg src_alpha_ctl;
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struct vop_reg alpha_pre_mul;
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struct vop_reg alpha_mode;
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struct vop_reg alpha_en;
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struct vop_reg channel;
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};
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struct vop_win_yuv2yuv_data {
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uint32_t base;
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const struct vop_yuv2yuv_phy *phy;
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struct vop_reg y2r_en;
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};
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struct vop_win_data {
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uint32_t base;
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const struct vop_win_phy *phy;
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enum drm_plane_type type;
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};
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struct vop_data {
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uint32_t version;
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const struct vop_intr *intr;
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const struct vop_common *common;
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const struct vop_misc *misc;
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const struct vop_modeset *modeset;
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const struct vop_output *output;
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const struct vop_afbc *afbc;
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const struct vop_win_yuv2yuv_data *win_yuv2yuv;
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const struct vop_win_data *win;
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unsigned int win_size;
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unsigned int lut_size;
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#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
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#define VOP_FEATURE_INTERNAL_RGB BIT(1)
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u64 feature;
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};
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/* interrupt define */
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#define DSP_HOLD_VALID_INTR (1 << 0)
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#define FS_INTR (1 << 1)
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#define LINE_FLAG_INTR (1 << 2)
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#define BUS_ERROR_INTR (1 << 3)
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#define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
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LINE_FLAG_INTR | BUS_ERROR_INTR)
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#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
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#define FS_INTR_EN(x) ((x) << 5)
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#define LINE_FLAG_INTR_EN(x) ((x) << 6)
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#define BUS_ERROR_INTR_EN(x) ((x) << 7)
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#define DSP_HOLD_VALID_INTR_MASK (1 << 4)
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#define FS_INTR_MASK (1 << 5)
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#define LINE_FLAG_INTR_MASK (1 << 6)
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#define BUS_ERROR_INTR_MASK (1 << 7)
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#define INTR_CLR_SHIFT 8
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#define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
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#define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
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#define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
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#define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
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#define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
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#define DSP_LINE_NUM_MASK (0x1fff << 12)
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/* src alpha ctrl define */
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#define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
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#define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
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#define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
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#define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
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#define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
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#define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
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#define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
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#define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
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/* dst alpha ctrl define */
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#define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
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/*
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* display output interface supported by rockchip lcdc
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*/
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#define ROCKCHIP_OUT_MODE_P888 0
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#define ROCKCHIP_OUT_MODE_P666 1
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#define ROCKCHIP_OUT_MODE_P565 2
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/* for use special outface */
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#define ROCKCHIP_OUT_MODE_AAAA 15
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/* output flags */
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#define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0)
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enum alpha_mode {
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ALPHA_STRAIGHT,
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ALPHA_INVERSE,
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};
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enum global_blend_mode {
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ALPHA_GLOBAL,
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ALPHA_PER_PIX,
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ALPHA_PER_PIX_GLOBAL,
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};
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enum alpha_cal_mode {
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ALPHA_SATURATION,
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ALPHA_NO_SATURATION,
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};
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enum color_mode {
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ALPHA_SRC_PRE_MUL,
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ALPHA_SRC_NO_PRE_MUL,
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};
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enum factor_mode {
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ALPHA_ZERO,
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ALPHA_ONE,
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ALPHA_SRC,
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ALPHA_SRC_INVERSE,
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ALPHA_SRC_GLOBAL,
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};
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enum scale_mode {
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SCALE_NONE = 0x0,
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SCALE_UP = 0x1,
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SCALE_DOWN = 0x2
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};
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enum lb_mode {
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LB_YUV_3840X5 = 0x0,
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LB_YUV_2560X8 = 0x1,
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LB_RGB_3840X2 = 0x2,
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LB_RGB_2560X4 = 0x3,
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LB_RGB_1920X5 = 0x4,
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LB_RGB_1280X8 = 0x5
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};
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enum sacle_up_mode {
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SCALE_UP_BIL = 0x0,
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SCALE_UP_BIC = 0x1
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};
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enum scale_down_mode {
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SCALE_DOWN_BIL = 0x0,
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SCALE_DOWN_AVG = 0x1
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};
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enum dither_down_mode {
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RGB888_TO_RGB565 = 0x0,
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RGB888_TO_RGB666 = 0x1
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};
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enum dither_down_mode_sel {
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DITHER_DOWN_ALLEGRO = 0x0,
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DITHER_DOWN_FRC = 0x1
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};
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enum vop_pol {
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HSYNC_POSITIVE = 0,
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VSYNC_POSITIVE = 1,
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DEN_NEGATIVE = 2
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};
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#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
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#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
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#define SCL_MAX_VSKIPLINES 4
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#define MIN_SCL_FT_AFTER_VSKIP 1
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static inline uint16_t scl_cal_scale(int src, int dst, int shift)
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{
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return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
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}
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static inline uint16_t scl_cal_scale2(int src, int dst)
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{
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return ((src - 1) << 12) / (dst - 1);
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}
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#define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
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#define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
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#define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
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static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
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int vskiplines)
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{
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int act_height;
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act_height = DIV_ROUND_UP(src_h, vskiplines);
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if (act_height == dst_h)
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return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
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return GET_SCL_FT_BILI_DN(act_height, dst_h);
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}
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static inline enum scale_mode scl_get_scl_mode(int src, int dst)
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{
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if (src < dst)
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return SCALE_UP;
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else if (src > dst)
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return SCALE_DOWN;
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return SCALE_NONE;
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}
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static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
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{
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uint32_t vskiplines;
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for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
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if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
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break;
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return vskiplines;
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}
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static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
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{
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int lb_mode;
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if (is_yuv) {
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if (width > 1280)
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lb_mode = LB_YUV_3840X5;
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else
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lb_mode = LB_YUV_2560X8;
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} else {
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if (width > 2560)
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lb_mode = LB_RGB_3840X2;
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else if (width > 1920)
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lb_mode = LB_RGB_2560X4;
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else
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lb_mode = LB_RGB_1920X5;
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}
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return lb_mode;
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}
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extern const struct component_ops vop_component_ops;
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#endif /* _ROCKCHIP_DRM_VOP_H */
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