724 lines
22 KiB
C
724 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/i2c.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_of.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_print.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_simple_kms_helper.h>
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#include "sun4i_backend.h"
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#include "sun4i_crtc.h"
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#include "sun4i_drv.h"
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#include "sun4i_hdmi.h"
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static inline struct sun4i_hdmi *
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drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
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{
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return container_of(encoder, struct sun4i_hdmi,
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encoder);
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}
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static inline struct sun4i_hdmi *
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drm_connector_to_sun4i_hdmi(struct drm_connector *connector)
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{
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return container_of(connector, struct sun4i_hdmi,
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connector);
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}
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static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
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struct drm_display_mode *mode)
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{
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struct hdmi_avi_infoframe frame;
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u8 buffer[17];
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int i, ret;
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ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
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&hdmi->connector, mode);
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if (ret < 0) {
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DRM_ERROR("Failed to get infoframes from mode\n");
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return ret;
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}
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ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
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if (ret < 0) {
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DRM_ERROR("Failed to pack infoframes\n");
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return ret;
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}
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for (i = 0; i < sizeof(buffer); i++)
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writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i));
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return 0;
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}
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static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct drm_display_mode *mode = &crtc_state->mode;
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if (mode->flags & DRM_MODE_FLAG_DBLCLK)
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return -EINVAL;
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return 0;
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}
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static void sun4i_hdmi_disable(struct drm_encoder *encoder)
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{
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struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
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u32 val;
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DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
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val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
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val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
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writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
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clk_disable_unprepare(hdmi->tmds_clk);
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}
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static void sun4i_hdmi_enable(struct drm_encoder *encoder)
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{
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struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
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struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
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struct drm_display_info *display = &hdmi->connector.display_info;
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u32 val = 0;
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DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
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clk_prepare_enable(hdmi->tmds_clk);
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sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
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val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
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val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
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writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
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val = SUN4I_HDMI_VID_CTRL_ENABLE;
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if (display->is_hdmi)
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val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
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writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
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}
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static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
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unsigned int x, y;
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u32 val;
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clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
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clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
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/* Set input sync enable */
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writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
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hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
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/*
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* Setup output pad (?) controls
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*
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* This is done here instead of at probe/bind time because
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* the controller seems to toggle some of the bits on its own.
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*
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* We can't just initialize the register there, we need to
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* protect the clock bits that have already been read out and
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* cached by the clock framework.
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*/
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val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
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val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
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val |= hdmi->variant->pad_ctrl1_init_val;
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writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
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val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
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/* Setup timing registers */
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writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
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SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
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hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
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x = mode->htotal - mode->hsync_start;
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y = mode->vtotal - mode->vsync_start;
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writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
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hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
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x = mode->hsync_start - mode->hdisplay;
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y = mode->vsync_start - mode->vdisplay;
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writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
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hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
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x = mode->hsync_end - mode->hsync_start;
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y = mode->vsync_end - mode->vsync_start;
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writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
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hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG);
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val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK;
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if (mode->flags & DRM_MODE_FLAG_PHSYNC)
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val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC;
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if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC;
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writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
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}
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static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder,
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const struct drm_display_mode *mode)
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{
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struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
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unsigned long rate = mode->clock * 1000;
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unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */
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long rounded_rate;
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/* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */
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if (rate > 165000000)
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return MODE_CLOCK_HIGH;
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rounded_rate = clk_round_rate(hdmi->tmds_clk, rate);
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if (rounded_rate > 0 &&
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max_t(unsigned long, rounded_rate, rate) -
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min_t(unsigned long, rounded_rate, rate) < diff)
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return MODE_OK;
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return MODE_NOCLOCK;
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}
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static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
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.atomic_check = sun4i_hdmi_atomic_check,
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.disable = sun4i_hdmi_disable,
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.enable = sun4i_hdmi_enable,
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.mode_set = sun4i_hdmi_mode_set,
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.mode_valid = sun4i_hdmi_mode_valid,
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};
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static int sun4i_hdmi_get_modes(struct drm_connector *connector)
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{
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struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
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struct edid *edid;
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int ret;
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edid = drm_get_edid(connector, hdmi->ddc_i2c ?: hdmi->i2c);
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if (!edid)
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return 0;
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DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
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connector->display_info.is_hdmi ? "an HDMI" : "a DVI");
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drm_connector_update_edid_property(connector, edid);
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cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
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ret = drm_add_edid_modes(connector, edid);
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kfree(edid);
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return ret;
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}
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static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev)
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{
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struct device_node *phandle, *remote;
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struct i2c_adapter *ddc;
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remote = of_graph_get_remote_node(dev->of_node, 1, -1);
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if (!remote)
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return ERR_PTR(-EINVAL);
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phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0);
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of_node_put(remote);
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if (!phandle)
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return ERR_PTR(-ENODEV);
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ddc = of_get_i2c_adapter_by_node(phandle);
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of_node_put(phandle);
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if (!ddc)
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return ERR_PTR(-EPROBE_DEFER);
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return ddc;
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}
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static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = {
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.get_modes = sun4i_hdmi_get_modes,
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};
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static enum drm_connector_status
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sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force)
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{
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struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
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unsigned long reg;
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reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG);
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if (!(reg & SUN4I_HDMI_HPD_HIGH)) {
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cec_phys_addr_invalidate(hdmi->cec_adap);
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return connector_status_disconnected;
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}
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return connector_status_connected;
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}
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static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = {
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.detect = sun4i_hdmi_connector_detect,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = drm_connector_cleanup,
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.reset = drm_atomic_helper_connector_reset,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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#ifdef CONFIG_DRM_SUN4I_HDMI_CEC
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static int sun4i_hdmi_cec_pin_read(struct cec_adapter *adap)
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{
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struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
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return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
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}
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static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap)
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{
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struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
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/* Start driving the CEC pin low */
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writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
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}
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static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap)
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{
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struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
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/*
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* Stop driving the CEC pin, the pull up will take over
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* unless another CEC device is driving the pin low.
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*/
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writel(0, hdmi->base + SUN4I_HDMI_CEC);
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}
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static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
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.read = sun4i_hdmi_cec_pin_read,
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.low = sun4i_hdmi_cec_pin_low,
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.high = sun4i_hdmi_cec_pin_high,
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};
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#endif
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#define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0))
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#define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0))
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/* Only difference from sun5i is AMP is 4 instead of 6 */
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static const struct sun4i_hdmi_variant sun4i_variant = {
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.pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
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SUN4I_HDMI_PAD_CTRL0_CKEN |
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SUN4I_HDMI_PAD_CTRL0_PWENG |
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SUN4I_HDMI_PAD_CTRL0_PWEND |
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SUN4I_HDMI_PAD_CTRL0_PWENC |
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SUN4I_HDMI_PAD_CTRL0_LDODEN |
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SUN4I_HDMI_PAD_CTRL0_LDOCEN |
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SUN4I_HDMI_PAD_CTRL0_BIASEN,
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.pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) |
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SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
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SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
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SUN4I_HDMI_PAD_CTRL1_REG_DEN |
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SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
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SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
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SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
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SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
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.pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
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SUN4I_HDMI_PLL_CTRL_CS(7) |
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SUN4I_HDMI_PLL_CTRL_CP_S(15) |
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SUN4I_HDMI_PLL_CTRL_S(7) |
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SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
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SUN4I_HDMI_PLL_CTRL_SDIV2 |
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SUN4I_HDMI_PLL_CTRL_LDO2_EN |
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SUN4I_HDMI_PLL_CTRL_LDO1_EN |
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SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
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SUN4I_HDMI_PLL_CTRL_BWS |
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SUN4I_HDMI_PLL_CTRL_PLL_EN,
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.ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
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.ddc_clk_pre_divider = 2,
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.ddc_clk_m_offset = 1,
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.field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
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.field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
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.field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
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.field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
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.field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
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.field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
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.field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
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.field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
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.field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
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.field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
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.field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
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.field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
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.field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
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.ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG,
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.ddc_fifo_has_dir = true,
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};
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static const struct sun4i_hdmi_variant sun5i_variant = {
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.pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
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SUN4I_HDMI_PAD_CTRL0_CKEN |
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SUN4I_HDMI_PAD_CTRL0_PWENG |
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SUN4I_HDMI_PAD_CTRL0_PWEND |
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SUN4I_HDMI_PAD_CTRL0_PWENC |
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SUN4I_HDMI_PAD_CTRL0_LDODEN |
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SUN4I_HDMI_PAD_CTRL0_LDOCEN |
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SUN4I_HDMI_PAD_CTRL0_BIASEN,
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.pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
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SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
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SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
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SUN4I_HDMI_PAD_CTRL1_REG_DEN |
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SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
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SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
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SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
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SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
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.pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
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SUN4I_HDMI_PLL_CTRL_CS(7) |
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SUN4I_HDMI_PLL_CTRL_CP_S(15) |
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SUN4I_HDMI_PLL_CTRL_S(7) |
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SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
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SUN4I_HDMI_PLL_CTRL_SDIV2 |
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SUN4I_HDMI_PLL_CTRL_LDO2_EN |
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SUN4I_HDMI_PLL_CTRL_LDO1_EN |
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SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
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SUN4I_HDMI_PLL_CTRL_BWS |
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SUN4I_HDMI_PLL_CTRL_PLL_EN,
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.ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
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.ddc_clk_pre_divider = 2,
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.ddc_clk_m_offset = 1,
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.field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
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.field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
|
|
.field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
|
|
.field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
|
|
.field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
|
|
.field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
|
|
.field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
|
|
.field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
|
|
.field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
|
|
.field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
|
|
.field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
|
|
.field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
|
|
.field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
|
|
|
|
.ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG,
|
|
.ddc_fifo_has_dir = true,
|
|
};
|
|
|
|
static const struct sun4i_hdmi_variant sun6i_variant = {
|
|
.has_ddc_parent_clk = true,
|
|
.has_reset_control = true,
|
|
.pad_ctrl0_init_val = 0xff |
|
|
SUN4I_HDMI_PAD_CTRL0_TXEN |
|
|
SUN4I_HDMI_PAD_CTRL0_CKEN |
|
|
SUN4I_HDMI_PAD_CTRL0_PWENG |
|
|
SUN4I_HDMI_PAD_CTRL0_PWEND |
|
|
SUN4I_HDMI_PAD_CTRL0_PWENC |
|
|
SUN4I_HDMI_PAD_CTRL0_LDODEN |
|
|
SUN4I_HDMI_PAD_CTRL0_LDOCEN,
|
|
.pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
|
|
SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) |
|
|
SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
|
|
SUN4I_HDMI_PAD_CTRL1_REG_DEN |
|
|
SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
|
|
SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
|
|
SUN4I_HDMI_PAD_CTRL1_PWSDT |
|
|
SUN4I_HDMI_PAD_CTRL1_PWSCK |
|
|
SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
|
|
SUN4I_HDMI_PAD_CTRL1_AMP_OPT |
|
|
SUN4I_HDMI_PAD_CTRL1_UNKNOWN,
|
|
.pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
|
|
SUN4I_HDMI_PLL_CTRL_CS(3) |
|
|
SUN4I_HDMI_PLL_CTRL_CP_S(10) |
|
|
SUN4I_HDMI_PLL_CTRL_S(4) |
|
|
SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
|
|
SUN4I_HDMI_PLL_CTRL_SDIV2 |
|
|
SUN4I_HDMI_PLL_CTRL_LDO2_EN |
|
|
SUN4I_HDMI_PLL_CTRL_LDO1_EN |
|
|
SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
|
|
SUN4I_HDMI_PLL_CTRL_PLL_EN,
|
|
|
|
.ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6),
|
|
.ddc_clk_pre_divider = 1,
|
|
.ddc_clk_m_offset = 2,
|
|
|
|
.tmds_clk_div_offset = 1,
|
|
|
|
.field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0),
|
|
.field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27),
|
|
.field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31),
|
|
.field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31),
|
|
.field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7),
|
|
.field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8),
|
|
.field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18),
|
|
.field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
|
|
.field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
|
|
.field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25),
|
|
.field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2),
|
|
.field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6),
|
|
.field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4),
|
|
|
|
.ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG,
|
|
.ddc_fifo_thres_incl = true,
|
|
};
|
|
|
|
static const struct regmap_config sun4i_hdmi_regmap_config = {
|
|
.reg_bits = 32,
|
|
.val_bits = 32,
|
|
.reg_stride = 4,
|
|
.max_register = 0x580,
|
|
};
|
|
|
|
static int sun4i_hdmi_bind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct drm_device *drm = data;
|
|
struct cec_connector_info conn_info;
|
|
struct sun4i_drv *drv = drm->dev_private;
|
|
struct sun4i_hdmi *hdmi;
|
|
u32 reg;
|
|
int ret;
|
|
|
|
hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
|
|
if (!hdmi)
|
|
return -ENOMEM;
|
|
dev_set_drvdata(dev, hdmi);
|
|
hdmi->dev = dev;
|
|
hdmi->drv = drv;
|
|
|
|
hdmi->variant = of_device_get_match_data(dev);
|
|
if (!hdmi->variant)
|
|
return -EINVAL;
|
|
|
|
hdmi->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(hdmi->base)) {
|
|
dev_err(dev, "Couldn't map the HDMI encoder registers\n");
|
|
return PTR_ERR(hdmi->base);
|
|
}
|
|
|
|
if (hdmi->variant->has_reset_control) {
|
|
hdmi->reset = devm_reset_control_get(dev, NULL);
|
|
if (IS_ERR(hdmi->reset)) {
|
|
dev_err(dev, "Couldn't get the HDMI reset control\n");
|
|
return PTR_ERR(hdmi->reset);
|
|
}
|
|
|
|
ret = reset_control_deassert(hdmi->reset);
|
|
if (ret) {
|
|
dev_err(dev, "Couldn't deassert HDMI reset\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
hdmi->bus_clk = devm_clk_get(dev, "ahb");
|
|
if (IS_ERR(hdmi->bus_clk)) {
|
|
dev_err(dev, "Couldn't get the HDMI bus clock\n");
|
|
ret = PTR_ERR(hdmi->bus_clk);
|
|
goto err_assert_reset;
|
|
}
|
|
clk_prepare_enable(hdmi->bus_clk);
|
|
|
|
hdmi->mod_clk = devm_clk_get(dev, "mod");
|
|
if (IS_ERR(hdmi->mod_clk)) {
|
|
dev_err(dev, "Couldn't get the HDMI mod clock\n");
|
|
ret = PTR_ERR(hdmi->mod_clk);
|
|
goto err_disable_bus_clk;
|
|
}
|
|
clk_prepare_enable(hdmi->mod_clk);
|
|
|
|
hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
|
|
if (IS_ERR(hdmi->pll0_clk)) {
|
|
dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
|
|
ret = PTR_ERR(hdmi->pll0_clk);
|
|
goto err_disable_mod_clk;
|
|
}
|
|
|
|
hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
|
|
if (IS_ERR(hdmi->pll1_clk)) {
|
|
dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
|
|
ret = PTR_ERR(hdmi->pll1_clk);
|
|
goto err_disable_mod_clk;
|
|
}
|
|
|
|
hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base,
|
|
&sun4i_hdmi_regmap_config);
|
|
if (IS_ERR(hdmi->regmap)) {
|
|
dev_err(dev, "Couldn't create HDMI encoder regmap\n");
|
|
ret = PTR_ERR(hdmi->regmap);
|
|
goto err_disable_mod_clk;
|
|
}
|
|
|
|
ret = sun4i_tmds_create(hdmi);
|
|
if (ret) {
|
|
dev_err(dev, "Couldn't create the TMDS clock\n");
|
|
goto err_disable_mod_clk;
|
|
}
|
|
|
|
if (hdmi->variant->has_ddc_parent_clk) {
|
|
hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
|
|
if (IS_ERR(hdmi->ddc_parent_clk)) {
|
|
dev_err(dev, "Couldn't get the HDMI DDC clock\n");
|
|
ret = PTR_ERR(hdmi->ddc_parent_clk);
|
|
goto err_disable_mod_clk;
|
|
}
|
|
} else {
|
|
hdmi->ddc_parent_clk = hdmi->tmds_clk;
|
|
}
|
|
|
|
writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
|
|
|
|
writel(hdmi->variant->pad_ctrl0_init_val,
|
|
hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
|
|
|
|
reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
|
|
reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
|
|
reg |= hdmi->variant->pll_ctrl_init_val;
|
|
writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
|
|
|
|
ret = sun4i_hdmi_i2c_create(dev, hdmi);
|
|
if (ret) {
|
|
dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
|
|
goto err_disable_mod_clk;
|
|
}
|
|
|
|
hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev);
|
|
if (IS_ERR(hdmi->ddc_i2c)) {
|
|
ret = PTR_ERR(hdmi->ddc_i2c);
|
|
if (ret == -ENODEV)
|
|
hdmi->ddc_i2c = NULL;
|
|
else
|
|
goto err_del_i2c_adapter;
|
|
}
|
|
|
|
drm_encoder_helper_add(&hdmi->encoder,
|
|
&sun4i_hdmi_helper_funcs);
|
|
ret = drm_simple_encoder_init(drm, &hdmi->encoder,
|
|
DRM_MODE_ENCODER_TMDS);
|
|
if (ret) {
|
|
dev_err(dev, "Couldn't initialise the HDMI encoder\n");
|
|
goto err_put_ddc_i2c;
|
|
}
|
|
|
|
hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
|
|
dev->of_node);
|
|
if (!hdmi->encoder.possible_crtcs) {
|
|
ret = -EPROBE_DEFER;
|
|
goto err_put_ddc_i2c;
|
|
}
|
|
|
|
#ifdef CONFIG_DRM_SUN4I_HDMI_CEC
|
|
hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
|
|
hdmi, "sun4i", CEC_CAP_DEFAULTS | CEC_CAP_CONNECTOR_INFO);
|
|
ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
|
|
if (ret < 0)
|
|
goto err_cleanup_connector;
|
|
writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
|
|
hdmi->base + SUN4I_HDMI_CEC);
|
|
#endif
|
|
|
|
drm_connector_helper_add(&hdmi->connector,
|
|
&sun4i_hdmi_connector_helper_funcs);
|
|
ret = drm_connector_init_with_ddc(drm, &hdmi->connector,
|
|
&sun4i_hdmi_connector_funcs,
|
|
DRM_MODE_CONNECTOR_HDMIA,
|
|
hdmi->ddc_i2c);
|
|
if (ret) {
|
|
dev_err(dev,
|
|
"Couldn't initialise the HDMI connector\n");
|
|
goto err_cleanup_connector;
|
|
}
|
|
cec_fill_conn_info_from_drm(&conn_info, &hdmi->connector);
|
|
cec_s_conn_info(hdmi->cec_adap, &conn_info);
|
|
|
|
/* There is no HPD interrupt, so we need to poll the controller */
|
|
hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
|
|
DRM_CONNECTOR_POLL_DISCONNECT;
|
|
|
|
ret = cec_register_adapter(hdmi->cec_adap, dev);
|
|
if (ret < 0)
|
|
goto err_cleanup_connector;
|
|
drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
|
|
|
|
return 0;
|
|
|
|
err_cleanup_connector:
|
|
cec_delete_adapter(hdmi->cec_adap);
|
|
drm_encoder_cleanup(&hdmi->encoder);
|
|
err_put_ddc_i2c:
|
|
i2c_put_adapter(hdmi->ddc_i2c);
|
|
err_del_i2c_adapter:
|
|
i2c_del_adapter(hdmi->i2c);
|
|
err_disable_mod_clk:
|
|
clk_disable_unprepare(hdmi->mod_clk);
|
|
err_disable_bus_clk:
|
|
clk_disable_unprepare(hdmi->bus_clk);
|
|
err_assert_reset:
|
|
reset_control_assert(hdmi->reset);
|
|
return ret;
|
|
}
|
|
|
|
static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
|
|
|
|
cec_unregister_adapter(hdmi->cec_adap);
|
|
i2c_del_adapter(hdmi->i2c);
|
|
i2c_put_adapter(hdmi->ddc_i2c);
|
|
clk_disable_unprepare(hdmi->mod_clk);
|
|
clk_disable_unprepare(hdmi->bus_clk);
|
|
}
|
|
|
|
static const struct component_ops sun4i_hdmi_ops = {
|
|
.bind = sun4i_hdmi_bind,
|
|
.unbind = sun4i_hdmi_unbind,
|
|
};
|
|
|
|
static int sun4i_hdmi_probe(struct platform_device *pdev)
|
|
{
|
|
return component_add(&pdev->dev, &sun4i_hdmi_ops);
|
|
}
|
|
|
|
static int sun4i_hdmi_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &sun4i_hdmi_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id sun4i_hdmi_of_table[] = {
|
|
{ .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, },
|
|
{ .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
|
|
{ .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
|
|
|
|
static struct platform_driver sun4i_hdmi_driver = {
|
|
.probe = sun4i_hdmi_probe,
|
|
.remove = sun4i_hdmi_remove,
|
|
.driver = {
|
|
.name = "sun4i-hdmi",
|
|
.of_match_table = sun4i_hdmi_of_table,
|
|
},
|
|
};
|
|
module_platform_driver(sun4i_hdmi_driver);
|
|
|
|
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
|
|
MODULE_DESCRIPTION("Allwinner A10 HDMI Driver");
|
|
MODULE_LICENSE("GPL");
|