587 lines
13 KiB
C
587 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015, NVIDIA Corporation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/host1x.h>
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#include <linux/iommu.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <soc/tegra/pmc.h>
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#include "drm.h"
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#include "falcon.h"
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#include "vic.h"
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struct vic_config {
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const char *firmware;
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unsigned int version;
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bool supports_sid;
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};
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struct vic {
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struct falcon falcon;
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void __iomem *regs;
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struct tegra_drm_client client;
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struct host1x_channel *channel;
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struct device *dev;
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struct clk *clk;
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struct reset_control *rst;
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bool can_use_context;
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/* Platform configuration */
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const struct vic_config *config;
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};
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static inline struct vic *to_vic(struct tegra_drm_client *client)
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{
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return container_of(client, struct vic, client);
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}
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static void vic_writel(struct vic *vic, u32 value, unsigned int offset)
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{
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writel(value, vic->regs + offset);
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}
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static int vic_boot(struct vic *vic)
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{
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u32 fce_ucode_size, fce_bin_data_offset, stream_id;
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void *hdr;
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int err = 0;
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if (vic->config->supports_sid && tegra_dev_iommu_get_stream_id(vic->dev, &stream_id)) {
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u32 value;
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value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) |
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TRANSCFG_ATT(0, TRANSCFG_SID_HW);
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vic_writel(vic, value, VIC_TFBIF_TRANSCFG);
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/*
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* STREAMID0 is used for input/output buffers. Initialize it to SID_VIC in case
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* context isolation is not enabled, and SID_VIC is used for both firmware and
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* data buffers.
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*
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* If context isolation is enabled, it will be overridden by the SETSTREAMID
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* opcode as part of each job.
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*/
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vic_writel(vic, stream_id, VIC_THI_STREAMID0);
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/* STREAMID1 is used for firmware loading. */
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vic_writel(vic, stream_id, VIC_THI_STREAMID1);
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}
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/* setup clockgating registers */
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vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
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CG_IDLE_CG_EN |
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CG_WAKEUP_DLY_CNT(4),
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NV_PVIC_MISC_PRI_VIC_CG);
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err = falcon_boot(&vic->falcon);
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if (err < 0)
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return err;
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hdr = vic->falcon.firmware.virt;
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fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
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/* Old VIC firmware needs kernel help with setting up FCE microcode. */
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if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) {
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hdr = vic->falcon.firmware.virt +
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*(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
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fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
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falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
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fce_ucode_size);
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falcon_execute_method(
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&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
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(vic->falcon.firmware.iova + fce_bin_data_offset) >> 8);
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}
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err = falcon_wait_idle(&vic->falcon);
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if (err < 0) {
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dev_err(vic->dev,
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"failed to set application ID and FCE base\n");
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return err;
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}
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return 0;
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}
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static int vic_init(struct host1x_client *client)
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{
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struct tegra_drm_client *drm = host1x_to_drm_client(client);
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struct drm_device *dev = dev_get_drvdata(client->host);
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struct tegra_drm *tegra = dev->dev_private;
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struct vic *vic = to_vic(drm);
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int err;
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err = host1x_client_iommu_attach(client);
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if (err < 0 && err != -ENODEV) {
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dev_err(vic->dev, "failed to attach to domain: %d\n", err);
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return err;
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}
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vic->channel = host1x_channel_request(client);
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if (!vic->channel) {
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err = -ENOMEM;
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goto detach;
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}
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client->syncpts[0] = host1x_syncpt_request(client, 0);
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if (!client->syncpts[0]) {
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err = -ENOMEM;
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goto free_channel;
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}
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pm_runtime_enable(client->dev);
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pm_runtime_use_autosuspend(client->dev);
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pm_runtime_set_autosuspend_delay(client->dev, 500);
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err = tegra_drm_register_client(tegra, drm);
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if (err < 0)
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goto disable_rpm;
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/*
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* Inherit the DMA parameters (such as maximum segment size) from the
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* parent host1x device.
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*/
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client->dev->dma_parms = client->host->dma_parms;
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return 0;
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disable_rpm:
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pm_runtime_dont_use_autosuspend(client->dev);
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pm_runtime_force_suspend(client->dev);
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host1x_syncpt_put(client->syncpts[0]);
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free_channel:
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host1x_channel_put(vic->channel);
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detach:
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host1x_client_iommu_detach(client);
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return err;
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}
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static int vic_exit(struct host1x_client *client)
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{
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struct tegra_drm_client *drm = host1x_to_drm_client(client);
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struct drm_device *dev = dev_get_drvdata(client->host);
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struct tegra_drm *tegra = dev->dev_private;
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struct vic *vic = to_vic(drm);
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int err;
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/* avoid a dangling pointer just in case this disappears */
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client->dev->dma_parms = NULL;
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err = tegra_drm_unregister_client(tegra, drm);
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if (err < 0)
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return err;
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pm_runtime_dont_use_autosuspend(client->dev);
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pm_runtime_force_suspend(client->dev);
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host1x_syncpt_put(client->syncpts[0]);
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host1x_channel_put(vic->channel);
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host1x_client_iommu_detach(client);
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vic->channel = NULL;
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if (client->group) {
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dma_unmap_single(vic->dev, vic->falcon.firmware.phys,
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vic->falcon.firmware.size, DMA_TO_DEVICE);
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tegra_drm_free(tegra, vic->falcon.firmware.size,
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vic->falcon.firmware.virt,
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vic->falcon.firmware.iova);
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} else {
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dma_free_coherent(vic->dev, vic->falcon.firmware.size,
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vic->falcon.firmware.virt,
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vic->falcon.firmware.iova);
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}
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return 0;
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}
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static const struct host1x_client_ops vic_client_ops = {
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.init = vic_init,
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.exit = vic_exit,
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};
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static int vic_load_firmware(struct vic *vic)
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{
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struct host1x_client *client = &vic->client.base;
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struct tegra_drm *tegra = vic->client.drm;
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static DEFINE_MUTEX(lock);
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u32 fce_bin_data_offset;
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dma_addr_t iova;
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size_t size;
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void *virt;
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int err;
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mutex_lock(&lock);
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if (vic->falcon.firmware.virt) {
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err = 0;
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goto unlock;
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}
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err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
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if (err < 0)
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goto unlock;
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size = vic->falcon.firmware.size;
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if (!client->group) {
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virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL);
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if (!virt) {
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err = -ENOMEM;
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goto unlock;
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}
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} else {
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virt = tegra_drm_alloc(tegra, size, &iova);
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if (IS_ERR(virt)) {
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err = PTR_ERR(virt);
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goto unlock;
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}
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}
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vic->falcon.firmware.virt = virt;
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vic->falcon.firmware.iova = iova;
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err = falcon_load_firmware(&vic->falcon);
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if (err < 0)
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goto cleanup;
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/*
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* In this case we have received an IOVA from the shared domain, so we
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* need to make sure to get the physical address so that the DMA API
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* knows what memory pages to flush the cache for.
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*/
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if (client->group) {
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dma_addr_t phys;
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phys = dma_map_single(vic->dev, virt, size, DMA_TO_DEVICE);
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err = dma_mapping_error(vic->dev, phys);
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if (err < 0)
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goto cleanup;
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vic->falcon.firmware.phys = phys;
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}
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/*
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* Check if firmware is new enough to not require mapping firmware
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* to data buffer domains.
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*/
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fce_bin_data_offset = *(u32 *)(virt + VIC_UCODE_FCE_DATA_OFFSET);
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if (!vic->config->supports_sid) {
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vic->can_use_context = false;
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} else if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) {
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/*
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* Firmware will access FCE through STREAMID0, so context
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* isolation cannot be used.
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*/
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vic->can_use_context = false;
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dev_warn_once(vic->dev, "context isolation disabled due to old firmware\n");
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} else {
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vic->can_use_context = true;
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}
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unlock:
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mutex_unlock(&lock);
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return err;
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cleanup:
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if (!client->group)
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dma_free_coherent(vic->dev, size, virt, iova);
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else
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tegra_drm_free(tegra, size, virt, iova);
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mutex_unlock(&lock);
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return err;
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}
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static int __maybe_unused vic_runtime_resume(struct device *dev)
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{
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struct vic *vic = dev_get_drvdata(dev);
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int err;
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err = clk_prepare_enable(vic->clk);
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if (err < 0)
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return err;
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usleep_range(10, 20);
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err = reset_control_deassert(vic->rst);
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if (err < 0)
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goto disable;
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usleep_range(10, 20);
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err = vic_load_firmware(vic);
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if (err < 0)
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goto assert;
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err = vic_boot(vic);
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if (err < 0)
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goto assert;
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return 0;
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assert:
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reset_control_assert(vic->rst);
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disable:
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clk_disable_unprepare(vic->clk);
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return err;
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}
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static int __maybe_unused vic_runtime_suspend(struct device *dev)
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{
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struct vic *vic = dev_get_drvdata(dev);
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int err;
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host1x_channel_stop(vic->channel);
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err = reset_control_assert(vic->rst);
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if (err < 0)
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return err;
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usleep_range(2000, 4000);
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clk_disable_unprepare(vic->clk);
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return 0;
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}
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static int vic_open_channel(struct tegra_drm_client *client,
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struct tegra_drm_context *context)
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{
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struct vic *vic = to_vic(client);
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context->channel = host1x_channel_get(vic->channel);
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if (!context->channel)
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return -ENOMEM;
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return 0;
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}
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static void vic_close_channel(struct tegra_drm_context *context)
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{
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host1x_channel_put(context->channel);
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}
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static int vic_can_use_memory_ctx(struct tegra_drm_client *client, bool *supported)
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{
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struct vic *vic = to_vic(client);
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int err;
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/* This doesn't access HW so it's safe to call without powering up. */
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err = vic_load_firmware(vic);
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if (err < 0)
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return err;
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*supported = vic->can_use_context;
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return 0;
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}
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static const struct tegra_drm_client_ops vic_ops = {
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.open_channel = vic_open_channel,
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.close_channel = vic_close_channel,
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.submit = tegra_drm_submit,
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.get_streamid_offset = tegra_drm_get_streamid_offset_thi,
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.can_use_memory_ctx = vic_can_use_memory_ctx,
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};
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#define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
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static const struct vic_config vic_t124_config = {
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.firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
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.version = 0x40,
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.supports_sid = false,
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};
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#define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
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static const struct vic_config vic_t210_config = {
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.firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
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.version = 0x21,
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.supports_sid = false,
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};
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#define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin"
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static const struct vic_config vic_t186_config = {
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.firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE,
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.version = 0x18,
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.supports_sid = true,
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};
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#define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
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static const struct vic_config vic_t194_config = {
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.firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
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.version = 0x19,
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.supports_sid = true,
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};
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#define NVIDIA_TEGRA_234_VIC_FIRMWARE "nvidia/tegra234/vic.bin"
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static const struct vic_config vic_t234_config = {
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.firmware = NVIDIA_TEGRA_234_VIC_FIRMWARE,
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.version = 0x23,
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.supports_sid = true,
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};
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static const struct of_device_id tegra_vic_of_match[] = {
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{ .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
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{ .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
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{ .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
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{ .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
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{ .compatible = "nvidia,tegra234-vic", .data = &vic_t234_config },
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{ },
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};
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MODULE_DEVICE_TABLE(of, tegra_vic_of_match);
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static int vic_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct host1x_syncpt **syncpts;
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struct vic *vic;
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int err;
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/* inherit DMA mask from host1x parent */
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err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
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return err;
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}
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vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL);
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if (!vic)
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return -ENOMEM;
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vic->config = of_device_get_match_data(dev);
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syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
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if (!syncpts)
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return -ENOMEM;
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vic->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(vic->regs))
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return PTR_ERR(vic->regs);
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vic->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(vic->clk)) {
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dev_err(&pdev->dev, "failed to get clock\n");
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return PTR_ERR(vic->clk);
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}
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err = clk_set_rate(vic->clk, ULONG_MAX);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to set clock rate\n");
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return err;
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}
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if (!dev->pm_domain) {
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vic->rst = devm_reset_control_get(dev, "vic");
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if (IS_ERR(vic->rst)) {
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dev_err(&pdev->dev, "failed to get reset\n");
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return PTR_ERR(vic->rst);
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}
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}
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vic->falcon.dev = dev;
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vic->falcon.regs = vic->regs;
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err = falcon_init(&vic->falcon);
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if (err < 0)
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return err;
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platform_set_drvdata(pdev, vic);
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INIT_LIST_HEAD(&vic->client.base.list);
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vic->client.base.ops = &vic_client_ops;
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vic->client.base.dev = dev;
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vic->client.base.class = HOST1X_CLASS_VIC;
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vic->client.base.syncpts = syncpts;
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vic->client.base.num_syncpts = 1;
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vic->dev = dev;
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INIT_LIST_HEAD(&vic->client.list);
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vic->client.version = vic->config->version;
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vic->client.ops = &vic_ops;
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err = host1x_client_register(&vic->client.base);
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if (err < 0) {
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dev_err(dev, "failed to register host1x client: %d\n", err);
|
|
goto exit_falcon;
|
|
}
|
|
|
|
return 0;
|
|
|
|
exit_falcon:
|
|
falcon_exit(&vic->falcon);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int vic_remove(struct platform_device *pdev)
|
|
{
|
|
struct vic *vic = platform_get_drvdata(pdev);
|
|
int err;
|
|
|
|
err = host1x_client_unregister(&vic->client.base);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
|
|
err);
|
|
return err;
|
|
}
|
|
|
|
falcon_exit(&vic->falcon);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops vic_pm_ops = {
|
|
RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL)
|
|
SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
|
|
};
|
|
|
|
struct platform_driver tegra_vic_driver = {
|
|
.driver = {
|
|
.name = "tegra-vic",
|
|
.of_match_table = tegra_vic_of_match,
|
|
.pm = &vic_pm_ops
|
|
},
|
|
.probe = vic_probe,
|
|
.remove = vic_remove,
|
|
};
|
|
|
|
#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
|
|
MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE);
|
|
#endif
|
|
#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
|
|
MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
|
|
#endif
|
|
#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
|
|
MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE);
|
|
#endif
|
|
#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
|
|
MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE);
|
|
#endif
|
|
#if IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
|
|
MODULE_FIRMWARE(NVIDIA_TEGRA_234_VIC_FIRMWARE);
|
|
#endif
|