475 lines
12 KiB
C
475 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* IIO driver for Texas Instruments ADS7924 ADC, 12-bit, 4-Channels, I2C
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*
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* Author: Hugo Villeneuve <hvilleneuve@dimonoff.com>
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* Copyright 2022 DimOnOff
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*
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* based on iio/adc/ti-ads1015.c
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* Copyright (c) 2016, Intel Corporation.
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*
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* Datasheet: https://www.ti.com/lit/gpn/ads7924
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*/
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/types.h>
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#define ADS7924_CHANNELS 4
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#define ADS7924_BITS 12
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#define ADS7924_DATA_SHIFT 4
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/* Registers. */
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#define ADS7924_MODECNTRL_REG 0x00
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#define ADS7924_INTCNTRL_REG 0x01
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#define ADS7924_DATA0_U_REG 0x02
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#define ADS7924_DATA0_L_REG 0x03
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#define ADS7924_DATA1_U_REG 0x04
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#define ADS7924_DATA1_L_REG 0x05
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#define ADS7924_DATA2_U_REG 0x06
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#define ADS7924_DATA2_L_REG 0x07
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#define ADS7924_DATA3_U_REG 0x08
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#define ADS7924_DATA3_L_REG 0x09
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#define ADS7924_ULR0_REG 0x0A
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#define ADS7924_LLR0_REG 0x0B
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#define ADS7924_ULR1_REG 0x0C
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#define ADS7924_LLR1_REG 0x0D
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#define ADS7924_ULR2_REG 0x0E
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#define ADS7924_LLR2_REG 0x0F
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#define ADS7924_ULR3_REG 0x10
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#define ADS7924_LLR3_REG 0x11
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#define ADS7924_INTCONFIG_REG 0x12
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#define ADS7924_SLPCONFIG_REG 0x13
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#define ADS7924_ACQCONFIG_REG 0x14
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#define ADS7924_PWRCONFIG_REG 0x15
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#define ADS7924_RESET_REG 0x16
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/*
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* Register address INC bit: when set to '1', the register address is
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* automatically incremented after every register read which allows convenient
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* reading of multiple registers. Set INC to '0' when reading a single register.
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*/
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#define ADS7924_AUTO_INCREMENT_BIT BIT(7)
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#define ADS7924_MODECNTRL_MODE_MASK GENMASK(7, 2)
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#define ADS7924_MODECNTRL_SEL_MASK GENMASK(1, 0)
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#define ADS7924_CFG_INTPOL_BIT 1
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#define ADS7924_CFG_INTTRIG_BIT 0
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#define ADS7924_CFG_INTPOL_MASK BIT(ADS7924_CFG_INTPOL_BIT)
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#define ADS7924_CFG_INTTRIG_MASK BIT(ADS7924_CFG_INTTRIG_BIT)
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/* Interrupt pin polarity */
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#define ADS7924_CFG_INTPOL_LOW 0
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#define ADS7924_CFG_INTPOL_HIGH 1
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/* Interrupt pin signaling */
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#define ADS7924_CFG_INTTRIG_LEVEL 0
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#define ADS7924_CFG_INTTRIG_EDGE 1
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/* Mode control values */
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#define ADS7924_MODECNTRL_IDLE 0x00
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#define ADS7924_MODECNTRL_AWAKE 0x20
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#define ADS7924_MODECNTRL_MANUAL_SINGLE 0x30
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#define ADS7924_MODECNTRL_MANUAL_SCAN 0x32
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#define ADS7924_MODECNTRL_AUTO_SINGLE 0x31
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#define ADS7924_MODECNTRL_AUTO_SCAN 0x33
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#define ADS7924_MODECNTRL_AUTO_SINGLE_SLEEP 0x39
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#define ADS7924_MODECNTRL_AUTO_SCAN_SLEEP 0x3B
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#define ADS7924_MODECNTRL_AUTO_BURST_SLEEP 0x3F
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#define ADS7924_ACQTIME_MASK GENMASK(4, 0)
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#define ADS7924_PWRUPTIME_MASK GENMASK(4, 0)
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/*
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* The power-up time is allowed to elapse whenever the device has been shutdown
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* in idle mode. Power-up time can allow external circuits, such as an
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* operational amplifier, between the MUXOUT and ADCIN pins to turn on.
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* The nominal time programmed by the PUTIME[4:0] register bits is given by:
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* t PU = PWRUPTIME[4:0] × 2 μs
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* If a power-up time is not required, set the bits to '0' to effectively bypass.
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*/
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#define ADS7924_PWRUPTIME_US 0 /* Bypass (0us). */
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/*
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* Acquisition Time according to ACQTIME[4:0] register bits.
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* The Acquisition Time is given by:
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* t ACQ = (ACQTIME[4:0] × 2 μs) + 6 μs
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* Using default value of 0 for ACQTIME[4:0] results in a minimum acquisition
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* time of 6us.
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*/
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#define ADS7924_ACQTIME_US 6
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/* The conversion time is always 4μs and cannot be programmed by the user. */
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#define ADS7924_CONVTIME_US 4
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#define ADS7924_TOTAL_CONVTIME_US (ADS7924_PWRUPTIME_US + ADS7924_ACQTIME_US + \
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ADS7924_CONVTIME_US)
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#define ADS7924_V_CHAN(_chan, _addr) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = _chan, \
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.address = _addr, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.datasheet_name = "AIN"#_chan, \
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}
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struct ads7924_data {
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struct device *dev;
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struct regmap *regmap;
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struct regulator *vref_reg;
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/* GPIO descriptor for device hard-reset pin. */
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struct gpio_desc *reset_gpio;
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/*
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* Protects ADC ops, e.g: concurrent sysfs/buffered
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* data reads, configuration updates
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*/
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struct mutex lock;
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/*
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* Set to true when the ADC is switched to the continuous-conversion
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* mode and exits from a power-down state. This flag is used to avoid
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* getting the stale result from the conversion register.
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*/
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bool conv_invalid;
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};
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static bool ads7924_is_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case ADS7924_MODECNTRL_REG:
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case ADS7924_INTCNTRL_REG:
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case ADS7924_ULR0_REG:
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case ADS7924_LLR0_REG:
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case ADS7924_ULR1_REG:
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case ADS7924_LLR1_REG:
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case ADS7924_ULR2_REG:
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case ADS7924_LLR2_REG:
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case ADS7924_ULR3_REG:
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case ADS7924_LLR3_REG:
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case ADS7924_INTCONFIG_REG:
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case ADS7924_SLPCONFIG_REG:
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case ADS7924_ACQCONFIG_REG:
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case ADS7924_PWRCONFIG_REG:
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case ADS7924_RESET_REG:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config ads7924_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = ADS7924_RESET_REG,
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.writeable_reg = ads7924_is_writeable_reg,
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};
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static const struct iio_chan_spec ads7924_channels[] = {
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ADS7924_V_CHAN(0, ADS7924_DATA0_U_REG),
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ADS7924_V_CHAN(1, ADS7924_DATA1_U_REG),
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ADS7924_V_CHAN(2, ADS7924_DATA2_U_REG),
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ADS7924_V_CHAN(3, ADS7924_DATA3_U_REG),
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};
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static int ads7924_get_adc_result(struct ads7924_data *data,
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struct iio_chan_spec const *chan, int *val)
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{
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int ret;
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__be16 be_val;
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if (chan->channel < 0 || chan->channel >= ADS7924_CHANNELS)
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return -EINVAL;
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if (data->conv_invalid) {
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int conv_time;
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conv_time = ADS7924_TOTAL_CONVTIME_US;
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/* Allow 10% for internal clock inaccuracy. */
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conv_time += conv_time / 10;
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usleep_range(conv_time, conv_time + 1);
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data->conv_invalid = false;
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}
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ret = regmap_raw_read(data->regmap, ADS7924_AUTO_INCREMENT_BIT |
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chan->address, &be_val, sizeof(be_val));
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if (ret)
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return ret;
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*val = be16_to_cpu(be_val) >> ADS7924_DATA_SHIFT;
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return 0;
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}
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static int ads7924_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, int *val,
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int *val2, long mask)
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{
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int ret, vref_uv;
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struct ads7924_data *data = iio_priv(indio_dev);
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&data->lock);
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ret = ads7924_get_adc_result(data, chan, val);
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mutex_unlock(&data->lock);
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if (ret < 0)
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return ret;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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vref_uv = regulator_get_voltage(data->vref_reg);
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if (vref_uv < 0)
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return vref_uv;
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*val = vref_uv / 1000; /* Convert reg voltage to mV */
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*val2 = ADS7924_BITS;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
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static const struct iio_info ads7924_info = {
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.read_raw = ads7924_read_raw,
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};
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static int ads7924_get_channels_config(struct i2c_client *client,
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struct iio_dev *indio_dev)
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{
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struct ads7924_data *priv = iio_priv(indio_dev);
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struct device *dev = priv->dev;
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struct fwnode_handle *node;
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int num_channels = 0;
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device_for_each_child_node(dev, node) {
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u32 pval;
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unsigned int channel;
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if (fwnode_property_read_u32(node, "reg", &pval)) {
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dev_err(dev, "invalid reg on %pfw\n", node);
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continue;
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}
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channel = pval;
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if (channel >= ADS7924_CHANNELS) {
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dev_err(dev, "invalid channel index %d on %pfw\n",
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channel, node);
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continue;
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}
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num_channels++;
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}
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if (!num_channels)
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return -EINVAL;
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return 0;
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}
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static int ads7924_set_conv_mode(struct ads7924_data *data, int mode)
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{
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int ret;
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unsigned int mode_field;
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struct device *dev = data->dev;
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/*
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* When switching between modes, be sure to first select the Awake mode
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* and then switch to the desired mode. This procedure ensures the
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* internal control logic is properly synchronized.
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*/
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if (mode != ADS7924_MODECNTRL_IDLE) {
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mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK,
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ADS7924_MODECNTRL_AWAKE);
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ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG,
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ADS7924_MODECNTRL_MODE_MASK,
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mode_field);
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if (ret) {
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dev_err(dev, "failed to set awake mode (%pe)\n",
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ERR_PTR(ret));
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return ret;
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}
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}
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mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK, mode);
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ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG,
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ADS7924_MODECNTRL_MODE_MASK, mode_field);
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if (ret)
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dev_err(dev, "failed to set mode %d (%pe)\n", mode,
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ERR_PTR(ret));
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return ret;
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}
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static int ads7924_reset(struct iio_dev *indio_dev)
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{
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struct ads7924_data *data = iio_priv(indio_dev);
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if (data->reset_gpio) {
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gpiod_set_value(data->reset_gpio, 1); /* Assert. */
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/* Educated guess: assert time not specified in datasheet... */
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mdelay(100);
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gpiod_set_value(data->reset_gpio, 0); /* Deassert. */
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return 0;
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}
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/*
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* A write of 10101010 to this register will generate a
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* software reset of the ADS7924.
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*/
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return regmap_write(data->regmap, ADS7924_RESET_REG, 0b10101010);
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};
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static void ads7924_reg_disable(void *data)
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{
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regulator_disable(data);
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}
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static void ads7924_set_idle_mode(void *data)
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{
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ads7924_set_conv_mode(data, ADS7924_MODECNTRL_IDLE);
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}
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static int ads7924_probe(struct i2c_client *client)
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{
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struct iio_dev *indio_dev;
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struct ads7924_data *data;
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struct device *dev = &client->dev;
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int ret;
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indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
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if (!indio_dev)
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return dev_err_probe(dev, -ENOMEM,
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"failed to allocate iio device\n");
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data = iio_priv(indio_dev);
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data->dev = dev;
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/* Initialize the reset GPIO as output with an initial value of 0. */
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data->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
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if (IS_ERR(data->reset_gpio))
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return dev_err_probe(dev, PTR_ERR(data->reset_gpio),
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"failed to get request reset GPIO\n");
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mutex_init(&data->lock);
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indio_dev->name = "ads7924";
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = ads7924_channels;
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indio_dev->num_channels = ARRAY_SIZE(ads7924_channels);
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indio_dev->info = &ads7924_info;
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ret = ads7924_get_channels_config(client, indio_dev);
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if (ret < 0)
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return dev_err_probe(dev, ret,
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"failed to get channels configuration\n");
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data->regmap = devm_regmap_init_i2c(client, &ads7924_regmap_config);
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if (IS_ERR(data->regmap))
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return dev_err_probe(dev, PTR_ERR(data->regmap),
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"failed to init regmap\n");
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data->vref_reg = devm_regulator_get(dev, "vref");
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if (IS_ERR(data->vref_reg))
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return dev_err_probe(dev, PTR_ERR(data->vref_reg),
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"failed to get vref regulator\n");
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ret = regulator_enable(data->vref_reg);
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if (ret)
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return dev_err_probe(dev, ret,
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"failed to enable regulator\n");
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ret = devm_add_action_or_reset(dev, ads7924_reg_disable, data->vref_reg);
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if (ret)
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return dev_err_probe(dev, ret,
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"failed to add regulator disable action\n");
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ret = ads7924_reset(indio_dev);
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if (ret < 0)
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return dev_err_probe(dev, ret,
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"failed to reset device\n");
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ret = ads7924_set_conv_mode(data, ADS7924_MODECNTRL_AUTO_SCAN);
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if (ret)
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return dev_err_probe(dev, ret,
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"failed to set conversion mode\n");
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ret = devm_add_action_or_reset(dev, ads7924_set_idle_mode, data);
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if (ret)
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return dev_err_probe(dev, ret,
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"failed to add idle mode action\n");
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/* Use minimum signal acquire time. */
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ret = regmap_update_bits(data->regmap, ADS7924_ACQCONFIG_REG,
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ADS7924_ACQTIME_MASK,
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FIELD_PREP(ADS7924_ACQTIME_MASK, 0));
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if (ret < 0)
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return dev_err_probe(dev, ret,
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"failed to configure signal acquire time\n");
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/* Disable power-up time. */
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ret = regmap_update_bits(data->regmap, ADS7924_PWRCONFIG_REG,
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ADS7924_PWRUPTIME_MASK,
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FIELD_PREP(ADS7924_PWRUPTIME_MASK, 0));
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if (ret < 0)
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return dev_err_probe(dev, ret,
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"failed to configure power-up time\n");
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data->conv_invalid = true;
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ret = devm_iio_device_register(dev, indio_dev);
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if (ret < 0)
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return dev_err_probe(dev, ret,
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"failed to register IIO device\n");
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return 0;
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}
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static const struct i2c_device_id ads7924_id[] = {
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{ "ads7924", 0 },
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{}
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};
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MODULE_DEVICE_TABLE(i2c, ads7924_id);
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static const struct of_device_id ads7924_of_match[] = {
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{ .compatible = "ti,ads7924", },
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{}
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};
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MODULE_DEVICE_TABLE(of, ads7924_of_match);
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static struct i2c_driver ads7924_driver = {
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.driver = {
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.name = "ads7924",
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.of_match_table = ads7924_of_match,
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},
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.probe_new = ads7924_probe,
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.id_table = ads7924_id,
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};
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module_i2c_driver(ads7924_driver);
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MODULE_AUTHOR("Hugo Villeneuve <hvilleneuve@dimonoff.com>");
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MODULE_DESCRIPTION("Texas Instruments ADS7924 ADC I2C driver");
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MODULE_LICENSE("GPL");
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