579 lines
14 KiB
C
579 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Ingenic JZ47xx NAND driver
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*
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* Copyright (c) 2015 Imagination Technologies
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* Author: Alex Smith <alex.smith@imgtec.com>
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/gpio/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/jz4780-nemc.h>
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#include "ingenic_ecc.h"
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#define DRV_NAME "ingenic-nand"
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struct jz_soc_info {
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unsigned long data_offset;
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unsigned long addr_offset;
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unsigned long cmd_offset;
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const struct mtd_ooblayout_ops *oob_layout;
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bool oob_first;
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};
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struct ingenic_nand_cs {
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unsigned int bank;
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void __iomem *base;
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};
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struct ingenic_nfc {
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struct device *dev;
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struct ingenic_ecc *ecc;
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const struct jz_soc_info *soc_info;
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struct nand_controller controller;
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unsigned int num_banks;
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struct list_head chips;
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struct ingenic_nand_cs cs[];
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};
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struct ingenic_nand {
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struct nand_chip chip;
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struct list_head chip_list;
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struct gpio_desc *busy_gpio;
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struct gpio_desc *wp_gpio;
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unsigned int reading: 1;
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};
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static inline struct ingenic_nand *to_ingenic_nand(struct mtd_info *mtd)
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{
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return container_of(mtd_to_nand(mtd), struct ingenic_nand, chip);
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}
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static inline struct ingenic_nfc *to_ingenic_nfc(struct nand_controller *ctrl)
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{
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return container_of(ctrl, struct ingenic_nfc, controller);
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}
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static int qi_lb60_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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if (section || !ecc->total)
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return -ERANGE;
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oobregion->length = ecc->total;
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oobregion->offset = 12;
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return 0;
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}
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static int qi_lb60_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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if (section)
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return -ERANGE;
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oobregion->length = mtd->oobsize - ecc->total - 12;
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oobregion->offset = 12 + ecc->total;
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return 0;
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}
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static const struct mtd_ooblayout_ops qi_lb60_ooblayout_ops = {
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.ecc = qi_lb60_ooblayout_ecc,
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.free = qi_lb60_ooblayout_free,
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};
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static int jz4725b_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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if (section || !ecc->total)
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return -ERANGE;
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oobregion->length = ecc->total;
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oobregion->offset = 3;
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return 0;
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}
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static int jz4725b_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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if (section)
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return -ERANGE;
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oobregion->length = mtd->oobsize - ecc->total - 3;
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oobregion->offset = 3 + ecc->total;
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return 0;
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}
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static const struct mtd_ooblayout_ops jz4725b_ooblayout_ops = {
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.ecc = jz4725b_ooblayout_ecc,
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.free = jz4725b_ooblayout_free,
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};
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static void ingenic_nand_ecc_hwctl(struct nand_chip *chip, int mode)
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{
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struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
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nand->reading = (mode == NAND_ECC_READ);
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}
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static int ingenic_nand_ecc_calculate(struct nand_chip *chip, const u8 *dat,
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u8 *ecc_code)
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{
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struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
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struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
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struct ingenic_ecc_params params;
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/*
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* Don't need to generate the ECC when reading, the ECC engine does it
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* for us as part of decoding/correction.
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*/
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if (nand->reading)
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return 0;
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params.size = nand->chip.ecc.size;
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params.bytes = nand->chip.ecc.bytes;
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params.strength = nand->chip.ecc.strength;
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return ingenic_ecc_calculate(nfc->ecc, ¶ms, dat, ecc_code);
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}
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static int ingenic_nand_ecc_correct(struct nand_chip *chip, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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{
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struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
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struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
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struct ingenic_ecc_params params;
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params.size = nand->chip.ecc.size;
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params.bytes = nand->chip.ecc.bytes;
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params.strength = nand->chip.ecc.strength;
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return ingenic_ecc_correct(nfc->ecc, ¶ms, dat, read_ecc);
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}
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static int ingenic_nand_attach_chip(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
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int eccbytes;
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if (chip->ecc.strength == 4) {
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/* JZ4740 uses 9 bytes of ECC to correct maximum 4 errors */
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chip->ecc.bytes = 9;
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} else {
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chip->ecc.bytes = fls((1 + 8) * chip->ecc.size) *
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(chip->ecc.strength / 8);
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}
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switch (chip->ecc.engine_type) {
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case NAND_ECC_ENGINE_TYPE_ON_HOST:
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if (!nfc->ecc) {
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dev_err(nfc->dev, "HW ECC selected, but ECC controller not found\n");
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return -ENODEV;
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}
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chip->ecc.hwctl = ingenic_nand_ecc_hwctl;
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chip->ecc.calculate = ingenic_nand_ecc_calculate;
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chip->ecc.correct = ingenic_nand_ecc_correct;
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fallthrough;
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case NAND_ECC_ENGINE_TYPE_SOFT:
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dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n",
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(nfc->ecc) ? "hardware ECC" : "software ECC",
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chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
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break;
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case NAND_ECC_ENGINE_TYPE_NONE:
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dev_info(nfc->dev, "not using ECC\n");
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break;
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default:
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dev_err(nfc->dev, "ECC mode %d not supported\n",
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chip->ecc.engine_type);
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return -EINVAL;
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}
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/* The NAND core will generate the ECC layout for SW ECC */
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if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
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return 0;
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/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
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eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
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if (eccbytes > mtd->oobsize - 2) {
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dev_err(nfc->dev,
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"invalid ECC config: required %d ECC bytes, but only %d are available",
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eccbytes, mtd->oobsize - 2);
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return -EINVAL;
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}
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/*
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* The generic layout for BBT markers will most likely overlap with our
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* ECC bytes in the OOB, so move the BBT markers outside the OOB area.
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*/
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if (chip->bbt_options & NAND_BBT_USE_FLASH)
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chip->bbt_options |= NAND_BBT_NO_OOB;
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if (nfc->soc_info->oob_first)
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chip->ecc.read_page = nand_read_page_hwecc_oob_first;
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/* For legacy reasons we use a different layout on the qi,lb60 board. */
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if (of_machine_is_compatible("qi,lb60"))
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mtd_set_ooblayout(mtd, &qi_lb60_ooblayout_ops);
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else if (nfc->soc_info->oob_layout)
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mtd_set_ooblayout(mtd, nfc->soc_info->oob_layout);
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else
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mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
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return 0;
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}
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static int ingenic_nand_exec_instr(struct nand_chip *chip,
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struct ingenic_nand_cs *cs,
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const struct nand_op_instr *instr)
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{
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struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
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struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
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unsigned int i;
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switch (instr->type) {
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case NAND_OP_CMD_INSTR:
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writeb(instr->ctx.cmd.opcode,
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cs->base + nfc->soc_info->cmd_offset);
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return 0;
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case NAND_OP_ADDR_INSTR:
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for (i = 0; i < instr->ctx.addr.naddrs; i++)
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writeb(instr->ctx.addr.addrs[i],
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cs->base + nfc->soc_info->addr_offset);
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return 0;
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case NAND_OP_DATA_IN_INSTR:
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if (instr->ctx.data.force_8bit ||
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!(chip->options & NAND_BUSWIDTH_16))
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ioread8_rep(cs->base + nfc->soc_info->data_offset,
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instr->ctx.data.buf.in,
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instr->ctx.data.len);
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else
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ioread16_rep(cs->base + nfc->soc_info->data_offset,
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instr->ctx.data.buf.in,
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instr->ctx.data.len);
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return 0;
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case NAND_OP_DATA_OUT_INSTR:
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if (instr->ctx.data.force_8bit ||
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!(chip->options & NAND_BUSWIDTH_16))
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iowrite8_rep(cs->base + nfc->soc_info->data_offset,
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instr->ctx.data.buf.out,
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instr->ctx.data.len);
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else
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iowrite16_rep(cs->base + nfc->soc_info->data_offset,
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instr->ctx.data.buf.out,
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instr->ctx.data.len);
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return 0;
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case NAND_OP_WAITRDY_INSTR:
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if (!nand->busy_gpio)
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return nand_soft_waitrdy(chip,
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instr->ctx.waitrdy.timeout_ms);
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return nand_gpio_waitrdy(chip, nand->busy_gpio,
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instr->ctx.waitrdy.timeout_ms);
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default:
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break;
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}
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return -EINVAL;
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}
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static int ingenic_nand_exec_op(struct nand_chip *chip,
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const struct nand_operation *op,
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bool check_only)
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{
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struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
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struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
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struct ingenic_nand_cs *cs;
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unsigned int i;
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int ret = 0;
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if (check_only)
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return 0;
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cs = &nfc->cs[op->cs];
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jz4780_nemc_assert(nfc->dev, cs->bank, true);
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for (i = 0; i < op->ninstrs; i++) {
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ret = ingenic_nand_exec_instr(chip, cs, &op->instrs[i]);
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if (ret)
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break;
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if (op->instrs[i].delay_ns)
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ndelay(op->instrs[i].delay_ns);
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}
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jz4780_nemc_assert(nfc->dev, cs->bank, false);
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return ret;
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}
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static const struct nand_controller_ops ingenic_nand_controller_ops = {
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.attach_chip = ingenic_nand_attach_chip,
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.exec_op = ingenic_nand_exec_op,
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};
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static int ingenic_nand_init_chip(struct platform_device *pdev,
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struct ingenic_nfc *nfc,
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struct device_node *np,
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unsigned int chipnr)
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{
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struct device *dev = &pdev->dev;
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struct ingenic_nand *nand;
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struct ingenic_nand_cs *cs;
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struct nand_chip *chip;
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struct mtd_info *mtd;
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const __be32 *reg;
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int ret = 0;
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cs = &nfc->cs[chipnr];
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reg = of_get_property(np, "reg", NULL);
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if (!reg)
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return -EINVAL;
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cs->bank = be32_to_cpu(*reg);
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jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
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cs->base = devm_platform_ioremap_resource(pdev, chipnr);
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if (IS_ERR(cs->base))
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return PTR_ERR(cs->base);
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nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
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if (!nand)
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return -ENOMEM;
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nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
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if (IS_ERR(nand->busy_gpio)) {
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ret = PTR_ERR(nand->busy_gpio);
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dev_err(dev, "failed to request busy GPIO: %d\n", ret);
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return ret;
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}
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/*
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* The rb-gpios semantics was undocumented and qi,lb60 (along with
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* the ingenic driver) got it wrong. The active state encodes the
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* NAND ready state, which is high level. Since there's no signal
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* inverter on this board, it should be active-high. Let's fix that
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* here for older DTs so we can re-use the generic nand_gpio_waitrdy()
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* helper, and be consistent with what other drivers do.
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*/
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if (of_machine_is_compatible("qi,lb60") &&
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gpiod_is_active_low(nand->busy_gpio))
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gpiod_toggle_active_low(nand->busy_gpio);
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nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
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if (IS_ERR(nand->wp_gpio)) {
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ret = PTR_ERR(nand->wp_gpio);
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dev_err(dev, "failed to request WP GPIO: %d\n", ret);
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return ret;
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}
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chip = &nand->chip;
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mtd = nand_to_mtd(chip);
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mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
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cs->bank);
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if (!mtd->name)
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return -ENOMEM;
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mtd->dev.parent = dev;
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chip->options = NAND_NO_SUBPAGE_WRITE;
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chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
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chip->controller = &nfc->controller;
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nand_set_flash_node(chip, np);
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chip->controller->ops = &ingenic_nand_controller_ops;
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ret = nand_scan(chip, 1);
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if (ret)
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return ret;
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ret = mtd_device_register(mtd, NULL, 0);
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if (ret) {
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nand_cleanup(chip);
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return ret;
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}
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list_add_tail(&nand->chip_list, &nfc->chips);
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return 0;
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}
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static void ingenic_nand_cleanup_chips(struct ingenic_nfc *nfc)
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{
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struct ingenic_nand *ingenic_chip;
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struct nand_chip *chip;
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int ret;
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while (!list_empty(&nfc->chips)) {
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ingenic_chip = list_first_entry(&nfc->chips,
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struct ingenic_nand, chip_list);
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chip = &ingenic_chip->chip;
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ret = mtd_device_unregister(nand_to_mtd(chip));
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WARN_ON(ret);
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nand_cleanup(chip);
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list_del(&ingenic_chip->chip_list);
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}
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}
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static int ingenic_nand_init_chips(struct ingenic_nfc *nfc,
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struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np;
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int i = 0;
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int ret;
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int num_chips = of_get_child_count(dev->of_node);
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if (num_chips > nfc->num_banks) {
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dev_err(dev, "found %d chips but only %d banks\n",
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num_chips, nfc->num_banks);
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return -EINVAL;
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}
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for_each_child_of_node(dev->of_node, np) {
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ret = ingenic_nand_init_chip(pdev, nfc, np, i);
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if (ret) {
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ingenic_nand_cleanup_chips(nfc);
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of_node_put(np);
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return ret;
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}
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i++;
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}
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return 0;
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}
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static int ingenic_nand_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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unsigned int num_banks;
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struct ingenic_nfc *nfc;
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int ret;
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num_banks = jz4780_nemc_num_banks(dev);
|
|
if (num_banks == 0) {
|
|
dev_err(dev, "no banks found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
nfc = devm_kzalloc(dev, struct_size(nfc, cs, num_banks), GFP_KERNEL);
|
|
if (!nfc)
|
|
return -ENOMEM;
|
|
|
|
nfc->soc_info = device_get_match_data(dev);
|
|
if (!nfc->soc_info)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* Check for ECC HW before we call nand_scan_ident, to prevent us from
|
|
* having to call it again if the ECC driver returns -EPROBE_DEFER.
|
|
*/
|
|
nfc->ecc = of_ingenic_ecc_get(dev->of_node);
|
|
if (IS_ERR(nfc->ecc))
|
|
return PTR_ERR(nfc->ecc);
|
|
|
|
nfc->dev = dev;
|
|
nfc->num_banks = num_banks;
|
|
|
|
nand_controller_init(&nfc->controller);
|
|
INIT_LIST_HEAD(&nfc->chips);
|
|
|
|
ret = ingenic_nand_init_chips(nfc, pdev);
|
|
if (ret) {
|
|
if (nfc->ecc)
|
|
ingenic_ecc_release(nfc->ecc);
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, nfc);
|
|
return 0;
|
|
}
|
|
|
|
static int ingenic_nand_remove(struct platform_device *pdev)
|
|
{
|
|
struct ingenic_nfc *nfc = platform_get_drvdata(pdev);
|
|
|
|
if (nfc->ecc)
|
|
ingenic_ecc_release(nfc->ecc);
|
|
|
|
ingenic_nand_cleanup_chips(nfc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct jz_soc_info jz4740_soc_info = {
|
|
.data_offset = 0x00000000,
|
|
.cmd_offset = 0x00008000,
|
|
.addr_offset = 0x00010000,
|
|
.oob_first = true,
|
|
};
|
|
|
|
static const struct jz_soc_info jz4725b_soc_info = {
|
|
.data_offset = 0x00000000,
|
|
.cmd_offset = 0x00008000,
|
|
.addr_offset = 0x00010000,
|
|
.oob_layout = &jz4725b_ooblayout_ops,
|
|
};
|
|
|
|
static const struct jz_soc_info jz4780_soc_info = {
|
|
.data_offset = 0x00000000,
|
|
.cmd_offset = 0x00400000,
|
|
.addr_offset = 0x00800000,
|
|
};
|
|
|
|
static const struct of_device_id ingenic_nand_dt_match[] = {
|
|
{ .compatible = "ingenic,jz4740-nand", .data = &jz4740_soc_info },
|
|
{ .compatible = "ingenic,jz4725b-nand", .data = &jz4725b_soc_info },
|
|
{ .compatible = "ingenic,jz4780-nand", .data = &jz4780_soc_info },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ingenic_nand_dt_match);
|
|
|
|
static struct platform_driver ingenic_nand_driver = {
|
|
.probe = ingenic_nand_probe,
|
|
.remove = ingenic_nand_remove,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = ingenic_nand_dt_match,
|
|
},
|
|
};
|
|
module_platform_driver(ingenic_nand_driver);
|
|
|
|
MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
|
|
MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
|
|
MODULE_DESCRIPTION("Ingenic JZ47xx NAND driver");
|
|
MODULE_LICENSE("GPL v2");
|