166 lines
5.4 KiB
C
166 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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* flexcan.c - FLEXCAN CAN controller driver
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*
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* Copyright (c) 2005-2006 Varma Electronics Oy
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* Copyright (c) 2009 Sascha Hauer, Pengutronix
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* Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
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* Copyright (c) 2014 David Jander, Protonic Holland
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* Copyright (C) 2022 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
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*
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* Based on code originally by Andrey Volkov <avolkov@varma-el.com>
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*
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*/
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#ifndef _FLEXCAN_H
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#define _FLEXCAN_H
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#include <linux/can/rx-offload.h>
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/* FLEXCAN hardware feature flags
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*
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* Below is some version info we got:
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* SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode MB
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* Filter? connected? Passive detection ption in MB Supported?
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* MCF5441X FlexCAN2 ? no yes no no no no 16
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* MX25 FlexCAN2 03.00.00.00 no no no no no no 64
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* MX28 FlexCAN2 03.00.04.00 yes yes no no no no 64
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* MX35 FlexCAN2 03.00.00.00 no no no no no no 64
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* MX53 FlexCAN2 03.00.00.00 yes no no no no no 64
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* MX6s FlexCAN3 10.00.12.00 yes yes no no yes no 64
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* MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes 64
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* MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes 64
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* VF610 FlexCAN3 ? no yes no yes yes? no 64
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* LS1021A FlexCAN2 03.00.04.00 no yes no no yes no 64
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* LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes 64
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*
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* Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
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*/
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/* [TR]WRN_INT not connected */
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#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
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/* Disable RX FIFO Global mask */
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#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
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/* Enable EACEN and RRS bit in ctrl2 */
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#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)
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/* Disable non-correctable errors interrupt and freeze mode */
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#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
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/* Use mailboxes (not FIFO) for RX path */
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#define FLEXCAN_QUIRK_USE_RX_MAILBOX BIT(5)
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/* No interrupt for error passive */
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#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
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/* default to BE register access */
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#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
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/* Setup stop mode with GPR to support wakeup */
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#define FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR BIT(8)
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/* Support CAN-FD mode */
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#define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
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/* support memory detection and correction */
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#define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)
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/* Setup stop mode with SCU firmware to support wakeup */
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#define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW BIT(11)
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/* Setup 3 separate interrupts, main, boff and err */
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#define FLEXCAN_QUIRK_NR_IRQ_3 BIT(12)
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/* Setup 16 mailboxes */
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#define FLEXCAN_QUIRK_NR_MB_16 BIT(13)
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/* Device supports RX via mailboxes */
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#define FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX BIT(14)
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/* Device supports RTR reception via mailboxes */
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#define FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR BIT(15)
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/* Device supports RX via FIFO */
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#define FLEXCAN_QUIRK_SUPPORT_RX_FIFO BIT(16)
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/* auto enter stop mode to support wakeup */
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#define FLEXCAN_QUIRK_AUTO_STOP_MODE BIT(17)
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struct flexcan_devtype_data {
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u32 quirks; /* quirks needed for different IP cores */
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};
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struct flexcan_stop_mode {
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struct regmap *gpr;
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u8 req_gpr;
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u8 req_bit;
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};
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struct flexcan_priv {
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struct can_priv can;
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struct can_rx_offload offload;
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struct device *dev;
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struct flexcan_regs __iomem *regs;
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struct flexcan_mb __iomem *tx_mb;
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struct flexcan_mb __iomem *tx_mb_reserved;
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u8 tx_mb_idx;
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u8 mb_count;
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u8 mb_size;
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u8 clk_src; /* clock source of CAN Protocol Engine */
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u8 scu_idx;
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u64 rx_mask;
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u64 tx_mask;
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u32 reg_ctrl_default;
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struct clk *clk_ipg;
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struct clk *clk_per;
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struct flexcan_devtype_data devtype_data;
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struct regulator *reg_xceiver;
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struct flexcan_stop_mode stm;
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int irq_boff;
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int irq_err;
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/* IPC handle when setup stop mode by System Controller firmware(scfw) */
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struct imx_sc_ipc *sc_ipc_handle;
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/* Read and Write APIs */
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u32 (*read)(void __iomem *addr);
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void (*write)(u32 val, void __iomem *addr);
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};
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extern const struct ethtool_ops flexcan_ethtool_ops;
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static inline bool
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flexcan_supports_rx_mailbox(const struct flexcan_priv *priv)
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{
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const u32 quirks = priv->devtype_data.quirks;
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return quirks & FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX;
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}
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static inline bool
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flexcan_supports_rx_mailbox_rtr(const struct flexcan_priv *priv)
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{
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const u32 quirks = priv->devtype_data.quirks;
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return (quirks & (FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
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FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR)) ==
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(FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
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FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR);
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}
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static inline bool
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flexcan_supports_rx_fifo(const struct flexcan_priv *priv)
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{
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const u32 quirks = priv->devtype_data.quirks;
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return quirks & FLEXCAN_QUIRK_SUPPORT_RX_FIFO;
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}
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static inline bool
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flexcan_active_rx_rtr(const struct flexcan_priv *priv)
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{
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const u32 quirks = priv->devtype_data.quirks;
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if (quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
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if (quirks & FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR)
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return true;
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} else {
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/* RX-FIFO is always RTR capable */
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return true;
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}
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return false;
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}
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#endif /* _FLEXCAN_H */
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