322 lines
9.2 KiB
C
322 lines
9.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
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/*
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* DSA driver for:
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* Hirschmann Hellcreek TSN switch.
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*
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* Copyright (C) 2019-2021 Linutronix GmbH
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* Author Kurt Kanzenbach <kurt@linutronix.de>
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*/
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#ifndef _HELLCREEK_H_
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#define _HELLCREEK_H_
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/workqueue.h>
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#include <linux/leds.h>
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#include <linux/platform_data/hirschmann-hellcreek.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/timecounter.h>
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#include <net/dsa.h>
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#include <net/pkt_sched.h>
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/* Ports:
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* - 0: CPU
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* - 1: Tunnel
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* - 2: TSN front port 1
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* - 3: TSN front port 2
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* - ...
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*/
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#define CPU_PORT 0
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#define TUNNEL_PORT 1
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#define HELLCREEK_VLAN_NO_MEMBER 0x0
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#define HELLCREEK_VLAN_UNTAGGED_MEMBER 0x1
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#define HELLCREEK_VLAN_TAGGED_MEMBER 0x3
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#define HELLCREEK_NUM_EGRESS_QUEUES 8
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#define HELLCREEK_DEFAULT_MAX_SDU 1536
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/* Register definitions */
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#define HR_MODID_C (0 * 2)
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#define HR_REL_L_C (1 * 2)
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#define HR_REL_H_C (2 * 2)
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#define HR_BLD_L_C (3 * 2)
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#define HR_BLD_H_C (4 * 2)
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#define HR_CTRL_C (5 * 2)
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#define HR_CTRL_C_READY BIT(14)
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#define HR_CTRL_C_TRANSITION BIT(13)
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#define HR_CTRL_C_ENABLE BIT(0)
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#define HR_PSEL (0xa6 * 2)
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#define HR_PSEL_PTWSEL_SHIFT 4
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#define HR_PSEL_PTWSEL_MASK GENMASK(5, 4)
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#define HR_PSEL_PRTCWSEL_SHIFT 0
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#define HR_PSEL_PRTCWSEL_MASK GENMASK(2, 0)
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#define HR_PTCFG (0xa7 * 2)
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#define HR_PTCFG_MLIMIT_EN BIT(13)
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#define HR_PTCFG_UMC_FLT BIT(10)
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#define HR_PTCFG_UUC_FLT BIT(9)
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#define HR_PTCFG_UNTRUST BIT(8)
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#define HR_PTCFG_TAG_REQUIRED BIT(7)
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#define HR_PTCFG_PPRIO_SHIFT 4
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#define HR_PTCFG_PPRIO_MASK GENMASK(6, 4)
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#define HR_PTCFG_INGRESSFLT BIT(3)
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#define HR_PTCFG_BLOCKED BIT(2)
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#define HR_PTCFG_LEARNING_EN BIT(1)
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#define HR_PTCFG_ADMIN_EN BIT(0)
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#define HR_PRTCCFG (0xa8 * 2)
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#define HR_PRTCCFG_PCP_TC_MAP_SHIFT 0
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#define HR_PRTCCFG_PCP_TC_MAP_MASK GENMASK(2, 0)
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#define HR_PTPRTCCFG (0xa9 * 2)
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#define HR_PTPRTCCFG_SET_QTRACK BIT(15)
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#define HR_PTPRTCCFG_REJECT BIT(14)
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#define HR_PTPRTCCFG_MAXSDU_SHIFT 0
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#define HR_PTPRTCCFG_MAXSDU_MASK GENMASK(10, 0)
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#define HR_CSEL (0x8d * 2)
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#define HR_CSEL_SHIFT 0
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#define HR_CSEL_MASK GENMASK(7, 0)
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#define HR_CRDL (0x8e * 2)
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#define HR_CRDH (0x8f * 2)
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#define HR_SWTRC_CFG (0x90 * 2)
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#define HR_SWTRC0 (0x91 * 2)
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#define HR_SWTRC1 (0x92 * 2)
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#define HR_PFREE (0x93 * 2)
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#define HR_MFREE (0x94 * 2)
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#define HR_FDBAGE (0x97 * 2)
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#define HR_FDBMAX (0x98 * 2)
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#define HR_FDBRDL (0x99 * 2)
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#define HR_FDBRDM (0x9a * 2)
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#define HR_FDBRDH (0x9b * 2)
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#define HR_FDBMDRD (0x9c * 2)
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#define HR_FDBMDRD_PORTMASK_SHIFT 0
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#define HR_FDBMDRD_PORTMASK_MASK GENMASK(3, 0)
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#define HR_FDBMDRD_AGE_SHIFT 4
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#define HR_FDBMDRD_AGE_MASK GENMASK(7, 4)
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#define HR_FDBMDRD_OBT BIT(8)
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#define HR_FDBMDRD_PASS_BLOCKED BIT(9)
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#define HR_FDBMDRD_STATIC BIT(11)
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#define HR_FDBMDRD_REPRIO_TC_SHIFT 12
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#define HR_FDBMDRD_REPRIO_TC_MASK GENMASK(14, 12)
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#define HR_FDBMDRD_REPRIO_EN BIT(15)
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#define HR_FDBWDL (0x9d * 2)
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#define HR_FDBWDM (0x9e * 2)
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#define HR_FDBWDH (0x9f * 2)
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#define HR_FDBWRM0 (0xa0 * 2)
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#define HR_FDBWRM0_PORTMASK_SHIFT 0
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#define HR_FDBWRM0_PORTMASK_MASK GENMASK(3, 0)
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#define HR_FDBWRM0_OBT BIT(8)
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#define HR_FDBWRM0_PASS_BLOCKED BIT(9)
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#define HR_FDBWRM0_REPRIO_TC_SHIFT 12
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#define HR_FDBWRM0_REPRIO_TC_MASK GENMASK(14, 12)
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#define HR_FDBWRM0_REPRIO_EN BIT(15)
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#define HR_FDBWRM1 (0xa1 * 2)
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#define HR_FDBWRCMD (0xa2 * 2)
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#define HR_FDBWRCMD_FDBDEL BIT(9)
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#define HR_SWCFG (0xa3 * 2)
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#define HR_SWCFG_GM_STATEMD BIT(15)
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#define HR_SWCFG_LAS_MODE_SHIFT 12
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#define HR_SWCFG_LAS_MODE_MASK GENMASK(13, 12)
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#define HR_SWCFG_LAS_OFF (0x00)
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#define HR_SWCFG_LAS_ON (0x01)
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#define HR_SWCFG_LAS_STATIC (0x10)
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#define HR_SWCFG_CT_EN BIT(11)
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#define HR_SWCFG_VLAN_UNAWARE BIT(10)
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#define HR_SWCFG_ALWAYS_OBT BIT(9)
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#define HR_SWCFG_FDBAGE_EN BIT(5)
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#define HR_SWCFG_FDBLRN_EN BIT(4)
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#define HR_SWSTAT (0xa4 * 2)
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#define HR_SWSTAT_FAIL BIT(4)
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#define HR_SWSTAT_BUSY BIT(0)
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#define HR_SWCMD (0xa5 * 2)
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#define HW_SWCMD_FLUSH BIT(0)
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#define HR_VIDCFG (0xaa * 2)
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#define HR_VIDCFG_VID_SHIFT 0
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#define HR_VIDCFG_VID_MASK GENMASK(11, 0)
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#define HR_VIDCFG_PVID BIT(12)
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#define HR_VIDMBRCFG (0xab * 2)
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#define HR_VIDMBRCFG_P0MBR_SHIFT 0
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#define HR_VIDMBRCFG_P0MBR_MASK GENMASK(1, 0)
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#define HR_VIDMBRCFG_P1MBR_SHIFT 2
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#define HR_VIDMBRCFG_P1MBR_MASK GENMASK(3, 2)
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#define HR_VIDMBRCFG_P2MBR_SHIFT 4
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#define HR_VIDMBRCFG_P2MBR_MASK GENMASK(5, 4)
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#define HR_VIDMBRCFG_P3MBR_SHIFT 6
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#define HR_VIDMBRCFG_P3MBR_MASK GENMASK(7, 6)
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#define HR_FEABITS0 (0xac * 2)
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#define HR_FEABITS0_FDBBINS_SHIFT 4
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#define HR_FEABITS0_FDBBINS_MASK GENMASK(7, 4)
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#define HR_FEABITS0_PCNT_SHIFT 8
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#define HR_FEABITS0_PCNT_MASK GENMASK(11, 8)
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#define HR_FEABITS0_MCNT_SHIFT 12
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#define HR_FEABITS0_MCNT_MASK GENMASK(15, 12)
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#define TR_QTRACK (0xb1 * 2)
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#define TR_TGDVER (0xb3 * 2)
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#define TR_TGDVER_REV_MIN_MASK GENMASK(7, 0)
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#define TR_TGDVER_REV_MIN_SHIFT 0
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#define TR_TGDVER_REV_MAJ_MASK GENMASK(15, 8)
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#define TR_TGDVER_REV_MAJ_SHIFT 8
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#define TR_TGDSEL (0xb4 * 2)
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#define TR_TGDSEL_TDGSEL_MASK GENMASK(1, 0)
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#define TR_TGDSEL_TDGSEL_SHIFT 0
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#define TR_TGDCTRL (0xb5 * 2)
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#define TR_TGDCTRL_GATE_EN BIT(0)
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#define TR_TGDCTRL_CYC_SNAP BIT(4)
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#define TR_TGDCTRL_SNAP_EST BIT(5)
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#define TR_TGDCTRL_ADMINGATESTATES_MASK GENMASK(15, 8)
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#define TR_TGDCTRL_ADMINGATESTATES_SHIFT 8
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#define TR_TGDSTAT0 (0xb6 * 2)
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#define TR_TGDSTAT1 (0xb7 * 2)
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#define TR_ESTWRL (0xb8 * 2)
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#define TR_ESTWRH (0xb9 * 2)
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#define TR_ESTCMD (0xba * 2)
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#define TR_ESTCMD_ESTSEC_MASK GENMASK(2, 0)
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#define TR_ESTCMD_ESTSEC_SHIFT 0
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#define TR_ESTCMD_ESTARM BIT(4)
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#define TR_ESTCMD_ESTSWCFG BIT(5)
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#define TR_EETWRL (0xbb * 2)
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#define TR_EETWRH (0xbc * 2)
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#define TR_EETCMD (0xbd * 2)
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#define TR_EETCMD_EETSEC_MASK GEMASK(2, 0)
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#define TR_EETCMD_EETSEC_SHIFT 0
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#define TR_EETCMD_EETARM BIT(4)
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#define TR_CTWRL (0xbe * 2)
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#define TR_CTWRH (0xbf * 2)
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#define TR_LCNSL (0xc1 * 2)
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#define TR_LCNSH (0xc2 * 2)
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#define TR_LCS (0xc3 * 2)
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#define TR_GCLDAT (0xc4 * 2)
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#define TR_GCLDAT_GCLWRGATES_MASK GENMASK(7, 0)
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#define TR_GCLDAT_GCLWRGATES_SHIFT 0
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#define TR_GCLDAT_GCLWRLAST BIT(8)
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#define TR_GCLDAT_GCLOVRI BIT(9)
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#define TR_GCLTIL (0xc5 * 2)
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#define TR_GCLTIH (0xc6 * 2)
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#define TR_GCLCMD (0xc7 * 2)
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#define TR_GCLCMD_GCLWRADR_MASK GENMASK(7, 0)
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#define TR_GCLCMD_GCLWRADR_SHIFT 0
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#define TR_GCLCMD_INIT_GATE_STATES_MASK GENMASK(15, 8)
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#define TR_GCLCMD_INIT_GATE_STATES_SHIFT 8
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struct hellcreek_counter {
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u8 offset;
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const char *name;
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};
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struct hellcreek;
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/* State flags for hellcreek_port_hwtstamp::state */
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enum {
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HELLCREEK_HWTSTAMP_ENABLED,
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HELLCREEK_HWTSTAMP_TX_IN_PROGRESS,
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};
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/* A structure to hold hardware timestamping information per port */
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struct hellcreek_port_hwtstamp {
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/* Timestamping state */
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unsigned long state;
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/* Resources for receive timestamping */
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struct sk_buff_head rx_queue; /* For synchronization messages */
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/* Resources for transmit timestamping */
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unsigned long tx_tstamp_start;
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struct sk_buff *tx_skb;
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/* Current timestamp configuration */
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struct hwtstamp_config tstamp_config;
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};
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struct hellcreek_port {
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struct hellcreek *hellcreek;
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unsigned long *vlan_dev_bitmap;
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int port;
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u16 ptcfg; /* ptcfg shadow */
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u64 *counter_values;
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/* Per-port timestamping resources */
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struct hellcreek_port_hwtstamp port_hwtstamp;
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/* Per-port Qbv schedule information */
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struct tc_taprio_qopt_offload *current_schedule;
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struct delayed_work schedule_work;
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};
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struct hellcreek_fdb_entry {
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size_t idx;
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unsigned char mac[ETH_ALEN];
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u8 portmask;
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u8 age;
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u8 is_obt;
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u8 pass_blocked;
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u8 is_static;
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u8 reprio_tc;
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u8 reprio_en;
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};
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struct hellcreek {
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const struct hellcreek_platform_data *pdata;
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struct device *dev;
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struct dsa_switch *ds;
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struct ptp_clock *ptp_clock;
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struct ptp_clock_info ptp_clock_info;
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struct hellcreek_port *ports;
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struct delayed_work overflow_work;
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struct led_classdev led_is_gm;
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struct led_classdev led_sync_good;
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struct mutex reg_lock; /* Switch IP register lock */
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struct mutex vlan_lock; /* VLAN bitmaps lock */
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struct mutex ptp_lock; /* PTP IP register lock */
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struct devlink_region *vlan_region;
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struct devlink_region *fdb_region;
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void __iomem *base;
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void __iomem *ptp_base;
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u16 swcfg; /* swcfg shadow */
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u8 *vidmbrcfg; /* vidmbrcfg shadow */
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u64 seconds; /* PTP seconds */
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u64 last_ts; /* Used for overflow detection */
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u16 status_out; /* ptp.status_out shadow */
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size_t fdb_entries;
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};
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/* A Qbv schedule can only started up to 8 seconds in the future. If the delta
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* between the base time and the current ptp time is larger than 8 seconds, then
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* use periodic work to check for the schedule to be started. The delayed work
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* cannot be armed directly to $base_time - 8 + X, because for large deltas the
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* PTP frequency matters.
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*/
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#define HELLCREEK_SCHEDULE_PERIOD (2 * HZ)
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#define dw_to_hellcreek_port(dw) \
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container_of(dw, struct hellcreek_port, schedule_work)
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/* Devlink resources */
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enum hellcreek_devlink_resource_id {
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HELLCREEK_DEVLINK_PARAM_ID_VLAN_TABLE,
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HELLCREEK_DEVLINK_PARAM_ID_FDB_TABLE,
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};
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struct hellcreek_devlink_vlan_entry {
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u16 vid;
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u16 member;
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};
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#endif /* _HELLCREEK_H_ */
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