391 lines
14 KiB
C
391 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/*
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* Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
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*/
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#ifndef _ENA_ETH_IO_H_
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#define _ENA_ETH_IO_H_
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enum ena_eth_io_l3_proto_index {
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ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
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ENA_ETH_IO_L3_PROTO_IPV4 = 8,
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ENA_ETH_IO_L3_PROTO_IPV6 = 11,
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ENA_ETH_IO_L3_PROTO_FCOE = 21,
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ENA_ETH_IO_L3_PROTO_ROCE = 22,
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};
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enum ena_eth_io_l4_proto_index {
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ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
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ENA_ETH_IO_L4_PROTO_TCP = 12,
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ENA_ETH_IO_L4_PROTO_UDP = 13,
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ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
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};
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struct ena_eth_io_tx_desc {
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/* 15:0 : length - Buffer length in bytes, must
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* include any packet trailers that the ENA supposed
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* to update like End-to-End CRC, Authentication GMAC
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* etc. This length must not include the
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* 'Push_Buffer' length. This length must not include
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* the 4-byte added in the end for 802.3 Ethernet FCS
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* 21:16 : req_id_hi - Request ID[15:10]
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* 22 : reserved22 - MBZ
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* 23 : meta_desc - MBZ
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* 24 : phase
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* 25 : reserved1 - MBZ
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* 26 : first - Indicates first descriptor in
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* transaction
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* 27 : last - Indicates last descriptor in
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* transaction
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* 28 : comp_req - Indicates whether completion
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* should be posted, after packet is transmitted.
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* Valid only for first descriptor
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* 30:29 : reserved29 - MBZ
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* 31 : reserved31 - MBZ
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*/
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u32 len_ctrl;
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/* 3:0 : l3_proto_idx - L3 protocol. This field
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* required when l3_csum_en,l3_csum or tso_en are set.
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* 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and
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* DF flags of the IPv4 header is 0. Otherwise must
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* be set to 1
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* 6:5 : reserved5
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* 7 : tso_en - Enable TSO, For TCP only.
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* 12:8 : l4_proto_idx - L4 protocol. This field need
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* to be set when l4_csum_en or tso_en are set.
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* 13 : l3_csum_en - enable IPv4 header checksum.
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* 14 : l4_csum_en - enable TCP/UDP checksum.
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* 15 : ethernet_fcs_dis - when set, the controller
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* will not append the 802.3 Ethernet Frame Check
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* Sequence to the packet
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* 16 : reserved16
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* 17 : l4_csum_partial - L4 partial checksum. when
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* set to 0, the ENA calculates the L4 checksum,
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* where the Destination Address required for the
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* TCP/UDP pseudo-header is taken from the actual
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* packet L3 header. when set to 1, the ENA doesn't
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* calculate the sum of the pseudo-header, instead,
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* the checksum field of the L4 is used instead. When
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* TSO enabled, the checksum of the pseudo-header
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* must not include the tcp length field. L4 partial
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* checksum should be used for IPv6 packet that
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* contains Routing Headers.
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* 20:18 : reserved18 - MBZ
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* 21 : reserved21 - MBZ
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* 31:22 : req_id_lo - Request ID[9:0]
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*/
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u32 meta_ctrl;
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u32 buff_addr_lo;
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/* address high and header size
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* 15:0 : addr_hi - Buffer Pointer[47:32]
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* 23:16 : reserved16_w2
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* 31:24 : header_length - Header length. For Low
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* Latency Queues, this fields indicates the number
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* of bytes written to the headers' memory. For
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* normal queues, if packet is TCP or UDP, and longer
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* than max_header_size, then this field should be
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* set to the sum of L4 header offset and L4 header
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* size(without options), otherwise, this field
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* should be set to 0. For both modes, this field
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* must not exceed the max_header_size.
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* max_header_size value is reported by the Max
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* Queues Feature descriptor
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*/
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u32 buff_addr_hi_hdr_sz;
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};
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struct ena_eth_io_tx_meta_desc {
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/* 9:0 : req_id_lo - Request ID[9:0]
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* 11:10 : reserved10 - MBZ
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* 12 : reserved12 - MBZ
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* 13 : reserved13 - MBZ
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* 14 : ext_valid - if set, offset fields in Word2
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* are valid Also MSS High in Word 0 and bits [31:24]
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* in Word 3
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* 15 : reserved15
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* 19:16 : mss_hi
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* 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1:
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* Extended Metadata Descriptor
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* 21 : meta_store - Store extended metadata in queue
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* cache
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* 22 : reserved22 - MBZ
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* 23 : meta_desc - MBO
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* 24 : phase
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* 25 : reserved25 - MBZ
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* 26 : first - Indicates first descriptor in
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* transaction
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* 27 : last - Indicates last descriptor in
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* transaction
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* 28 : comp_req - Indicates whether completion
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* should be posted, after packet is transmitted.
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* Valid only for first descriptor
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* 30:29 : reserved29 - MBZ
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* 31 : reserved31 - MBZ
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*/
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u32 len_ctrl;
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/* 5:0 : req_id_hi
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* 31:6 : reserved6 - MBZ
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*/
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u32 word1;
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/* 7:0 : l3_hdr_len
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* 15:8 : l3_hdr_off
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* 21:16 : l4_hdr_len_in_words - counts the L4 header
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* length in words. there is an explicit assumption
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* that L4 header appears right after L3 header and
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* L4 offset is based on l3_hdr_off+l3_hdr_len
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* 31:22 : mss_lo
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*/
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u32 word2;
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u32 reserved;
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};
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struct ena_eth_io_tx_cdesc {
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/* Request ID[15:0] */
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u16 req_id;
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u8 status;
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/* flags
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* 0 : phase
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* 7:1 : reserved1
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*/
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u8 flags;
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u16 sub_qid;
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u16 sq_head_idx;
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};
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struct ena_eth_io_rx_desc {
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/* In bytes. 0 means 64KB */
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u16 length;
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/* MBZ */
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u8 reserved2;
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/* 0 : phase
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* 1 : reserved1 - MBZ
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* 2 : first - Indicates first descriptor in
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* transaction
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* 3 : last - Indicates last descriptor in transaction
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* 4 : comp_req
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* 5 : reserved5 - MBO
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* 7:6 : reserved6 - MBZ
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*/
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u8 ctrl;
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u16 req_id;
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/* MBZ */
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u16 reserved6;
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u32 buff_addr_lo;
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u16 buff_addr_hi;
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/* MBZ */
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u16 reserved16_w3;
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};
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/* 4-word format Note: all ethernet parsing information are valid only when
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* last=1
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*/
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struct ena_eth_io_rx_cdesc_base {
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/* 4:0 : l3_proto_idx
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* 6:5 : src_vlan_cnt
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* 7 : reserved7 - MBZ
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* 12:8 : l4_proto_idx
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* 13 : l3_csum_err - when set, either the L3
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* checksum error detected, or, the controller didn't
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* validate the checksum. This bit is valid only when
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* l3_proto_idx indicates IPv4 packet
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* 14 : l4_csum_err - when set, either the L4
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* checksum error detected, or, the controller didn't
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* validate the checksum. This bit is valid only when
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* l4_proto_idx indicates TCP/UDP packet, and,
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* ipv4_frag is not set. This bit is valid only when
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* l4_csum_checked below is set.
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* 15 : ipv4_frag - Indicates IPv4 fragmented packet
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* 16 : l4_csum_checked - L4 checksum was verified
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* (could be OK or error), when cleared the status of
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* checksum is unknown
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* 23:17 : reserved17 - MBZ
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* 24 : phase
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* 25 : l3_csum2 - second checksum engine result
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* 26 : first - Indicates first descriptor in
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* transaction
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* 27 : last - Indicates last descriptor in
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* transaction
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* 29:28 : reserved28
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* 30 : buffer - 0: Metadata descriptor. 1: Buffer
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* Descriptor was used
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* 31 : reserved31
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*/
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u32 status;
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u16 length;
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u16 req_id;
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/* 32-bit hash result */
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u32 hash;
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u16 sub_qid;
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u8 offset;
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u8 reserved;
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};
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/* 8-word format */
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struct ena_eth_io_rx_cdesc_ext {
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struct ena_eth_io_rx_cdesc_base base;
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u32 buff_addr_lo;
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u16 buff_addr_hi;
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u16 reserved16;
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u32 reserved_w6;
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u32 reserved_w7;
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};
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struct ena_eth_io_intr_reg {
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/* 14:0 : rx_intr_delay
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* 29:15 : tx_intr_delay
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* 30 : intr_unmask
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* 31 : reserved
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*/
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u32 intr_control;
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};
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struct ena_eth_io_numa_node_cfg_reg {
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/* 7:0 : numa
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* 30:8 : reserved
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* 31 : enabled
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*/
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u32 numa_cfg;
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};
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/* tx_desc */
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#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
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#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
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#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
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#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
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#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
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#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
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#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
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#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
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#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
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#define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
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#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
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#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
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#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
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#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
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#define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
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#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
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#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
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#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
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#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
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#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
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#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
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#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
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#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
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#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
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#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
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#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
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#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
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#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
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#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
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#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
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#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
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#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
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#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
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/* tx_meta_desc */
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#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
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#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
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#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
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#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
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#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
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#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
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#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
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#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
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#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
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#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
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#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
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#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
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#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
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#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
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#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
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#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
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#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
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#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
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#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
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#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
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#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
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#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
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#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
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#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
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#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
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#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
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#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
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/* tx_cdesc */
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#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
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/* rx_desc */
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#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
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#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
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#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
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#define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
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#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
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#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
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#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
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/* rx_cdesc_base */
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#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
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#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
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#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
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#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
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#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
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#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
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#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
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#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
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#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
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#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
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#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
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#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16
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#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16)
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#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
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#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
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#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
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#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
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#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
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#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
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#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
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#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
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#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
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#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
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/* intr_reg */
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#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
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#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
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#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
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#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
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#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
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/* numa_node_cfg_reg */
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#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
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#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
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#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
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#endif /* _ENA_ETH_IO_H_ */
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