539 lines
18 KiB
C
539 lines
18 KiB
C
/*
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* AMD 10Gb Ethernet driver
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*
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* This file is available to you under your choice of the following two
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* licenses:
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*
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* License 1: GPLv2
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*
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* Copyright (c) 2016 Advanced Micro Devices, Inc.
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*
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* This file is free software; you may copy, redistribute and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or (at
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* your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* The Synopsys DWC ETHER XGMAC Software Driver and documentation
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* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
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* Inc. unless otherwise expressly agreed to in writing between Synopsys
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* and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product
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* under any End User Software License Agreement or Agreement for Licensed
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* Product with Synopsys or any supplement thereto. Permission is hereby
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* granted, free of charge, to any person obtaining a copy of this software
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* annotated with this license and the Software, to deal in the Software
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* without restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is furnished
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* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* License 2: Modified BSD
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*
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* Copyright (c) 2016 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* The Synopsys DWC ETHER XGMAC Software Driver and documentation
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* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
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* Inc. unless otherwise expressly agreed to in writing between Synopsys
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* and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product
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* under any End User Software License Agreement or Agreement for Licensed
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* Product with Synopsys or any supplement thereto. Permission is hereby
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* granted, free of charge, to any person obtaining a copy of this software
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* annotated with this license and the Software, to deal in the Software
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* without restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is furnished
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* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/pci.h>
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#include <linux/log2.h>
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#include "xgbe.h"
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#include "xgbe-common.h"
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static int xgbe_config_multi_msi(struct xgbe_prv_data *pdata)
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{
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unsigned int vector_count;
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unsigned int i, j;
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int ret;
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vector_count = XGBE_MSI_BASE_COUNT;
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vector_count += max(pdata->rx_ring_count,
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pdata->tx_ring_count);
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ret = pci_alloc_irq_vectors(pdata->pcidev, XGBE_MSI_MIN_COUNT,
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vector_count, PCI_IRQ_MSI | PCI_IRQ_MSIX);
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if (ret < 0) {
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dev_info(pdata->dev, "multi MSI/MSI-X enablement failed\n");
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return ret;
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}
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pdata->isr_as_tasklet = 1;
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pdata->irq_count = ret;
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pdata->dev_irq = pci_irq_vector(pdata->pcidev, 0);
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pdata->ecc_irq = pci_irq_vector(pdata->pcidev, 1);
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pdata->i2c_irq = pci_irq_vector(pdata->pcidev, 2);
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pdata->an_irq = pci_irq_vector(pdata->pcidev, 3);
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for (i = XGBE_MSI_BASE_COUNT, j = 0; i < ret; i++, j++)
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pdata->channel_irq[j] = pci_irq_vector(pdata->pcidev, i);
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pdata->channel_irq_count = j;
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pdata->per_channel_irq = 1;
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pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
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if (netif_msg_probe(pdata))
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dev_dbg(pdata->dev, "multi %s interrupts enabled\n",
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pdata->pcidev->msix_enabled ? "MSI-X" : "MSI");
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return 0;
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}
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static int xgbe_config_irqs(struct xgbe_prv_data *pdata)
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{
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int ret;
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ret = xgbe_config_multi_msi(pdata);
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if (!ret)
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goto out;
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ret = pci_alloc_irq_vectors(pdata->pcidev, 1, 1,
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PCI_IRQ_LEGACY | PCI_IRQ_MSI);
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if (ret < 0) {
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dev_info(pdata->dev, "single IRQ enablement failed\n");
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return ret;
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}
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pdata->isr_as_tasklet = pdata->pcidev->msi_enabled ? 1 : 0;
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pdata->irq_count = 1;
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pdata->channel_irq_count = 1;
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pdata->dev_irq = pci_irq_vector(pdata->pcidev, 0);
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pdata->ecc_irq = pci_irq_vector(pdata->pcidev, 0);
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pdata->i2c_irq = pci_irq_vector(pdata->pcidev, 0);
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pdata->an_irq = pci_irq_vector(pdata->pcidev, 0);
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if (netif_msg_probe(pdata))
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dev_dbg(pdata->dev, "single %s interrupt enabled\n",
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pdata->pcidev->msi_enabled ? "MSI" : "legacy");
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out:
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if (netif_msg_probe(pdata)) {
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unsigned int i;
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dev_dbg(pdata->dev, " dev irq=%d\n", pdata->dev_irq);
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dev_dbg(pdata->dev, " ecc irq=%d\n", pdata->ecc_irq);
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dev_dbg(pdata->dev, " i2c irq=%d\n", pdata->i2c_irq);
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dev_dbg(pdata->dev, " an irq=%d\n", pdata->an_irq);
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for (i = 0; i < pdata->channel_irq_count; i++)
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dev_dbg(pdata->dev, " dma%u irq=%d\n",
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i, pdata->channel_irq[i]);
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}
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return 0;
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}
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static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct xgbe_prv_data *pdata;
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struct device *dev = &pdev->dev;
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void __iomem * const *iomap_table;
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struct pci_dev *rdev;
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unsigned int ma_lo, ma_hi;
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unsigned int reg;
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int bar_mask;
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int ret;
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pdata = xgbe_alloc_pdata(dev);
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if (IS_ERR(pdata)) {
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ret = PTR_ERR(pdata);
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goto err_alloc;
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}
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pdata->pcidev = pdev;
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pci_set_drvdata(pdev, pdata);
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/* Get the version data */
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pdata->vdata = (struct xgbe_version_data *)id->driver_data;
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ret = pcim_enable_device(pdev);
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if (ret) {
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dev_err(dev, "pcim_enable_device failed\n");
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goto err_pci_enable;
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}
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/* Obtain the mmio areas for the device */
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bar_mask = pci_select_bars(pdev, IORESOURCE_MEM);
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ret = pcim_iomap_regions(pdev, bar_mask, XGBE_DRV_NAME);
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if (ret) {
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dev_err(dev, "pcim_iomap_regions failed\n");
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goto err_pci_enable;
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}
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iomap_table = pcim_iomap_table(pdev);
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if (!iomap_table) {
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dev_err(dev, "pcim_iomap_table failed\n");
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ret = -ENOMEM;
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goto err_pci_enable;
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}
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pdata->xgmac_regs = iomap_table[XGBE_XGMAC_BAR];
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if (!pdata->xgmac_regs) {
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dev_err(dev, "xgmac ioremap failed\n");
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ret = -ENOMEM;
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goto err_pci_enable;
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}
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pdata->xprop_regs = pdata->xgmac_regs + XGBE_MAC_PROP_OFFSET;
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pdata->xi2c_regs = pdata->xgmac_regs + XGBE_I2C_CTRL_OFFSET;
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if (netif_msg_probe(pdata)) {
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dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs);
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dev_dbg(dev, "xprop_regs = %p\n", pdata->xprop_regs);
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dev_dbg(dev, "xi2c_regs = %p\n", pdata->xi2c_regs);
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}
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pdata->xpcs_regs = iomap_table[XGBE_XPCS_BAR];
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if (!pdata->xpcs_regs) {
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dev_err(dev, "xpcs ioremap failed\n");
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ret = -ENOMEM;
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goto err_pci_enable;
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}
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if (netif_msg_probe(pdata))
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dev_dbg(dev, "xpcs_regs = %p\n", pdata->xpcs_regs);
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/* Set the PCS indirect addressing definition registers */
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rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
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if (rdev &&
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(rdev->vendor == PCI_VENDOR_ID_AMD) && (rdev->device == 0x15d0)) {
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pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
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pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
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} else if (rdev && (rdev->vendor == PCI_VENDOR_ID_AMD) &&
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(rdev->device == 0x14b5)) {
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pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF;
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pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT;
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/* Yellow Carp devices do not need cdr workaround */
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pdata->vdata->an_cdr_workaround = 0;
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/* Yellow Carp devices do not need rrc */
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pdata->vdata->enable_rrc = 0;
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} else {
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pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
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pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
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}
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pci_dev_put(rdev);
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/* Configure the PCS indirect addressing support */
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reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
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pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
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pdata->xpcs_window <<= 6;
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pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
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pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
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pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
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if (netif_msg_probe(pdata)) {
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dev_dbg(dev, "xpcs window def = %#010x\n",
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pdata->xpcs_window_def_reg);
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dev_dbg(dev, "xpcs window sel = %#010x\n",
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pdata->xpcs_window_sel_reg);
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dev_dbg(dev, "xpcs window = %#010x\n",
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pdata->xpcs_window);
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dev_dbg(dev, "xpcs window size = %#010x\n",
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pdata->xpcs_window_size);
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dev_dbg(dev, "xpcs window mask = %#010x\n",
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pdata->xpcs_window_mask);
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}
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pci_set_master(pdev);
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/* Enable all interrupts in the hardware */
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XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
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/* Retrieve the MAC address */
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ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
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ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
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pdata->mac_addr[0] = ma_lo & 0xff;
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pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
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pdata->mac_addr[2] = (ma_lo >> 16) & 0xff;
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pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
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pdata->mac_addr[4] = ma_hi & 0xff;
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pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
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if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID) ||
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!is_valid_ether_addr(pdata->mac_addr)) {
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dev_err(dev, "invalid mac address\n");
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ret = -EINVAL;
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goto err_pci_enable;
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}
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/* Clock settings */
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pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
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pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
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/* Set the DMA coherency values */
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pdata->coherent = 1;
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pdata->arcr = XGBE_DMA_PCI_ARCR;
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pdata->awcr = XGBE_DMA_PCI_AWCR;
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pdata->awarcr = XGBE_DMA_PCI_AWARCR;
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/* Read the port property registers */
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pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
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pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
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pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
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pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
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pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
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if (netif_msg_probe(pdata)) {
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dev_dbg(dev, "port property 0 = %#010x\n", pdata->pp0);
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dev_dbg(dev, "port property 1 = %#010x\n", pdata->pp1);
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dev_dbg(dev, "port property 2 = %#010x\n", pdata->pp2);
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dev_dbg(dev, "port property 3 = %#010x\n", pdata->pp3);
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dev_dbg(dev, "port property 4 = %#010x\n", pdata->pp4);
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}
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/* Set the maximum channels and queues */
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pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
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MAX_TX_DMA);
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pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
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MAX_RX_DMA);
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pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
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MAX_TX_QUEUES);
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pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
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MAX_RX_QUEUES);
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if (netif_msg_probe(pdata)) {
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dev_dbg(dev, "max tx/rx channel count = %u/%u\n",
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pdata->tx_max_channel_count,
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pdata->rx_max_channel_count);
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dev_dbg(dev, "max tx/rx hw queue count = %u/%u\n",
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pdata->tx_max_q_count, pdata->rx_max_q_count);
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}
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/* Set the hardware channel and queue counts */
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xgbe_set_counts(pdata);
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/* Set the maximum fifo amounts */
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pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
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TX_FIFO_SIZE);
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pdata->tx_max_fifo_size *= 16384;
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pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
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pdata->vdata->tx_max_fifo_size);
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pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
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RX_FIFO_SIZE);
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pdata->rx_max_fifo_size *= 16384;
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pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
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pdata->vdata->rx_max_fifo_size);
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if (netif_msg_probe(pdata))
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dev_dbg(dev, "max tx/rx max fifo size = %u/%u\n",
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pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
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/* Configure interrupt support */
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ret = xgbe_config_irqs(pdata);
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if (ret)
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goto err_pci_enable;
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/* Configure the netdev resource */
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ret = xgbe_config_netdev(pdata);
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if (ret)
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goto err_irq_vectors;
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netdev_notice(pdata->netdev, "net device enabled\n");
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return 0;
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err_irq_vectors:
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pci_free_irq_vectors(pdata->pcidev);
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err_pci_enable:
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xgbe_free_pdata(pdata);
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err_alloc:
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dev_notice(dev, "net device not enabled\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void xgbe_pci_remove(struct pci_dev *pdev)
|
|
{
|
|
struct xgbe_prv_data *pdata = pci_get_drvdata(pdev);
|
|
|
|
xgbe_deconfig_netdev(pdata);
|
|
|
|
pci_free_irq_vectors(pdata->pcidev);
|
|
|
|
/* Disable all interrupts in the hardware */
|
|
XP_IOWRITE(pdata, XP_INT_EN, 0x0);
|
|
|
|
xgbe_free_pdata(pdata);
|
|
}
|
|
|
|
static int __maybe_unused xgbe_pci_suspend(struct device *dev)
|
|
{
|
|
struct xgbe_prv_data *pdata = dev_get_drvdata(dev);
|
|
struct net_device *netdev = pdata->netdev;
|
|
int ret = 0;
|
|
|
|
if (netif_running(netdev))
|
|
ret = xgbe_powerdown(netdev, XGMAC_DRIVER_CONTEXT);
|
|
|
|
pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
|
|
pdata->lpm_ctrl |= MDIO_CTRL1_LPOWER;
|
|
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __maybe_unused xgbe_pci_resume(struct device *dev)
|
|
{
|
|
struct xgbe_prv_data *pdata = dev_get_drvdata(dev);
|
|
struct net_device *netdev = pdata->netdev;
|
|
int ret = 0;
|
|
|
|
XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
|
|
|
|
pdata->lpm_ctrl &= ~MDIO_CTRL1_LPOWER;
|
|
XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
|
|
|
|
if (netif_running(netdev)) {
|
|
ret = xgbe_powerup(netdev, XGMAC_DRIVER_CONTEXT);
|
|
|
|
/* Schedule a restart in case the link or phy state changed
|
|
* while we were powered down.
|
|
*/
|
|
schedule_work(&pdata->restart_work);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct xgbe_version_data xgbe_v2a = {
|
|
.init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
|
|
.xpcs_access = XGBE_XPCS_ACCESS_V2,
|
|
.mmc_64bit = 1,
|
|
.tx_max_fifo_size = 229376,
|
|
.rx_max_fifo_size = 229376,
|
|
.tx_tstamp_workaround = 1,
|
|
.ecc_support = 1,
|
|
.i2c_support = 1,
|
|
.irq_reissue_support = 1,
|
|
.tx_desc_prefetch = 5,
|
|
.rx_desc_prefetch = 5,
|
|
.an_cdr_workaround = 1,
|
|
.enable_rrc = 1,
|
|
};
|
|
|
|
static struct xgbe_version_data xgbe_v2b = {
|
|
.init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
|
|
.xpcs_access = XGBE_XPCS_ACCESS_V2,
|
|
.mmc_64bit = 1,
|
|
.tx_max_fifo_size = 65536,
|
|
.rx_max_fifo_size = 65536,
|
|
.tx_tstamp_workaround = 1,
|
|
.ecc_support = 1,
|
|
.i2c_support = 1,
|
|
.irq_reissue_support = 1,
|
|
.tx_desc_prefetch = 5,
|
|
.rx_desc_prefetch = 5,
|
|
.an_cdr_workaround = 1,
|
|
.enable_rrc = 1,
|
|
};
|
|
|
|
static const struct pci_device_id xgbe_pci_table[] = {
|
|
{ PCI_VDEVICE(AMD, 0x1458),
|
|
.driver_data = (kernel_ulong_t)&xgbe_v2a },
|
|
{ PCI_VDEVICE(AMD, 0x1459),
|
|
.driver_data = (kernel_ulong_t)&xgbe_v2b },
|
|
/* Last entry must be zero */
|
|
{ 0, }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, xgbe_pci_table);
|
|
|
|
static SIMPLE_DEV_PM_OPS(xgbe_pci_pm_ops, xgbe_pci_suspend, xgbe_pci_resume);
|
|
|
|
static struct pci_driver xgbe_driver = {
|
|
.name = XGBE_DRV_NAME,
|
|
.id_table = xgbe_pci_table,
|
|
.probe = xgbe_pci_probe,
|
|
.remove = xgbe_pci_remove,
|
|
.driver = {
|
|
.pm = &xgbe_pci_pm_ops,
|
|
}
|
|
};
|
|
|
|
int xgbe_pci_init(void)
|
|
{
|
|
return pci_register_driver(&xgbe_driver);
|
|
}
|
|
|
|
void xgbe_pci_exit(void)
|
|
{
|
|
pci_unregister_driver(&xgbe_driver);
|
|
}
|