278 lines
7.0 KiB
C
278 lines
7.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Marvell MCS driver
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*
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* Copyright (C) 2022 Marvell.
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*/
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#include "mcs.h"
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#include "mcs_reg.h"
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static struct mcs_ops cnf10kb_mcs_ops = {
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.mcs_set_hw_capabilities = cnf10kb_mcs_set_hw_capabilities,
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.mcs_parser_cfg = cnf10kb_mcs_parser_cfg,
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.mcs_tx_sa_mem_map_write = cnf10kb_mcs_tx_sa_mem_map_write,
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.mcs_rx_sa_mem_map_write = cnf10kb_mcs_rx_sa_mem_map_write,
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.mcs_flowid_secy_map = cnf10kb_mcs_flowid_secy_map,
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.mcs_bbe_intr_handler = cnf10kb_mcs_bbe_intr_handler,
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.mcs_pab_intr_handler = cnf10kb_mcs_pab_intr_handler,
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};
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struct mcs_ops *cnf10kb_get_mac_ops(void)
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{
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return &cnf10kb_mcs_ops;
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}
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void cnf10kb_mcs_set_hw_capabilities(struct mcs *mcs)
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{
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struct hwinfo *hw = mcs->hw;
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hw->tcam_entries = 64; /* TCAM entries */
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hw->secy_entries = 64; /* SecY entries */
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hw->sc_entries = 64; /* SC CAM entries */
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hw->sa_entries = 128; /* SA entries */
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hw->lmac_cnt = 4; /* lmacs/ports per mcs block */
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hw->mcs_x2p_intf = 1; /* x2p clabration intf */
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hw->mcs_blks = 7; /* MCS blocks */
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hw->ip_vec = MCS_CNF10KB_INT_VEC_IP; /* IP vector */
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}
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void cnf10kb_mcs_parser_cfg(struct mcs *mcs)
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{
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u64 reg, val;
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/* VLAN Ctag */
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val = (0x8100ull & 0xFFFF) | BIT_ULL(20) | BIT_ULL(22);
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reg = MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(0);
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mcs_reg_write(mcs, reg, val);
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reg = MCSX_PEX_TX_SLAVE_CUSTOM_TAGX(0);
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mcs_reg_write(mcs, reg, val);
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/* VLAN STag */
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val = (0x88a8ull & 0xFFFF) | BIT_ULL(20) | BIT_ULL(23);
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/* RX */
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reg = MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(1);
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mcs_reg_write(mcs, reg, val);
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/* TX */
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reg = MCSX_PEX_TX_SLAVE_CUSTOM_TAGX(1);
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mcs_reg_write(mcs, reg, val);
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/* Enable custom tage 0 and 1 and sectag */
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val = BIT_ULL(0) | BIT_ULL(1) | BIT_ULL(12);
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reg = MCSX_PEX_RX_SLAVE_ETYPE_ENABLE;
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mcs_reg_write(mcs, reg, val);
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reg = MCSX_PEX_TX_SLAVE_ETYPE_ENABLE;
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mcs_reg_write(mcs, reg, val);
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}
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void cnf10kb_mcs_flowid_secy_map(struct mcs *mcs, struct secy_mem_map *map, int dir)
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{
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u64 reg, val;
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val = (map->secy & 0x3F) | (map->ctrl_pkt & 0x1) << 6;
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if (dir == MCS_RX) {
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reg = MCSX_CPM_RX_SLAVE_SECY_MAP_MEMX(map->flow_id);
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} else {
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reg = MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_0X(map->flow_id);
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mcs_reg_write(mcs, reg, map->sci);
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val |= (map->sc & 0x3F) << 7;
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reg = MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_1X(map->flow_id);
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}
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mcs_reg_write(mcs, reg, val);
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}
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void cnf10kb_mcs_tx_sa_mem_map_write(struct mcs *mcs, struct mcs_tx_sc_sa_map *map)
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{
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u64 reg, val;
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val = (map->sa_index0 & 0x7F) | (map->sa_index1 & 0x7F) << 7;
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reg = MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(map->sc_id);
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mcs_reg_write(mcs, reg, val);
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reg = MCSX_CPM_TX_SLAVE_AUTO_REKEY_ENABLE_0;
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val = mcs_reg_read(mcs, reg);
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if (map->rekey_ena)
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val |= BIT_ULL(map->sc_id);
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else
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val &= ~BIT_ULL(map->sc_id);
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mcs_reg_write(mcs, reg, val);
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mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX0_VLDX(map->sc_id), map->sa_index0_vld);
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mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX1_VLDX(map->sc_id), map->sa_index1_vld);
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mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(map->sc_id), map->tx_sa_active);
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}
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void cnf10kb_mcs_rx_sa_mem_map_write(struct mcs *mcs, struct mcs_rx_sc_sa_map *map)
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{
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u64 val, reg;
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val = (map->sa_index & 0x7F) | (map->sa_in_use << 7);
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reg = MCSX_CPM_RX_SLAVE_SA_MAP_MEMX((4 * map->sc_id) + map->an);
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mcs_reg_write(mcs, reg, val);
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}
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int mcs_set_force_clk_en(struct mcs *mcs, bool set)
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{
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unsigned long timeout = jiffies + usecs_to_jiffies(2000);
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u64 val;
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val = mcs_reg_read(mcs, MCSX_MIL_GLOBAL);
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if (set) {
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val |= BIT_ULL(4);
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mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
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/* Poll till mcsx_mil_ip_gbl_status.mcs_ip_stats_ready value is 1 */
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while (!(mcs_reg_read(mcs, MCSX_MIL_IP_GBL_STATUS) & BIT_ULL(0))) {
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if (time_after(jiffies, timeout)) {
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dev_err(mcs->dev, "MCS set force clk enable failed\n");
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break;
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}
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}
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} else {
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val &= ~BIT_ULL(4);
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mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
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}
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return 0;
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}
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/* TX SA interrupt is raised only if autorekey is enabled.
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* MCS_CPM_TX_SLAVE_SA_MAP_MEM_0X[sc].tx_sa_active bit gets toggled if
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* one of two SAs mapped to SC gets expired. If tx_sa_active=0 implies
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* SA in SA_index1 got expired else SA in SA_index0 got expired.
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*/
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void cnf10kb_mcs_tx_pn_thresh_reached_handler(struct mcs *mcs)
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{
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struct mcs_intr_event event;
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struct rsrc_bmap *sc_bmap;
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unsigned long rekey_ena;
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u64 val, sa_status;
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int sc;
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sc_bmap = &mcs->tx.sc;
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event.mcs_id = mcs->mcs_id;
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event.intr_mask = MCS_CPM_TX_PN_THRESH_REACHED_INT;
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rekey_ena = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_AUTO_REKEY_ENABLE_0);
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for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) {
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/* Auto rekey is enable */
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if (!test_bit(sc, &rekey_ena))
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continue;
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sa_status = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(sc));
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/* Check if tx_sa_active status had changed */
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if (sa_status == mcs->tx_sa_active[sc])
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continue;
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/* SA_index0 is expired */
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val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc));
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if (sa_status)
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event.sa_id = val & 0x7F;
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else
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event.sa_id = (val >> 7) & 0x7F;
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event.pcifunc = mcs->tx.sa2pf_map[event.sa_id];
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mcs_add_intr_wq_entry(mcs, &event);
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}
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}
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void cnf10kb_mcs_tx_pn_wrapped_handler(struct mcs *mcs)
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{
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struct mcs_intr_event event = { 0 };
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struct rsrc_bmap *sc_bmap;
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u64 val;
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int sc;
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sc_bmap = &mcs->tx.sc;
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event.mcs_id = mcs->mcs_id;
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event.intr_mask = MCS_CPM_TX_PACKET_XPN_EQ0_INT;
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for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) {
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val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc));
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if (mcs->tx_sa_active[sc])
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/* SA_index1 was used and got expired */
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event.sa_id = (val >> 7) & 0x7F;
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else
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/* SA_index0 was used and got expired */
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event.sa_id = val & 0x7F;
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event.pcifunc = mcs->tx.sa2pf_map[event.sa_id];
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mcs_add_intr_wq_entry(mcs, &event);
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}
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}
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void cnf10kb_mcs_bbe_intr_handler(struct mcs *mcs, u64 intr,
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enum mcs_direction dir)
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{
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struct mcs_intr_event event = { 0 };
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int i;
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if (!(intr & MCS_BBE_INT_MASK))
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return;
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event.mcs_id = mcs->mcs_id;
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event.pcifunc = mcs->pf_map[0];
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for (i = 0; i < MCS_MAX_BBE_INT; i++) {
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if (!(intr & BIT_ULL(i)))
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continue;
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/* Lower nibble denotes data fifo overflow interrupts and
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* upper nibble indicates policy fifo overflow interrupts.
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*/
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if (intr & 0xFULL)
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event.intr_mask = (dir == MCS_RX) ?
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MCS_BBE_RX_DFIFO_OVERFLOW_INT :
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MCS_BBE_TX_DFIFO_OVERFLOW_INT;
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else
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event.intr_mask = (dir == MCS_RX) ?
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MCS_BBE_RX_PLFIFO_OVERFLOW_INT :
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MCS_BBE_TX_PLFIFO_OVERFLOW_INT;
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/* Notify the lmac_id info which ran into BBE fatal error */
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event.lmac_id = i & 0x3ULL;
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mcs_add_intr_wq_entry(mcs, &event);
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}
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}
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void cnf10kb_mcs_pab_intr_handler(struct mcs *mcs, u64 intr,
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enum mcs_direction dir)
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{
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struct mcs_intr_event event = { 0 };
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int i;
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if (!(intr & MCS_PAB_INT_MASK))
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return;
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event.mcs_id = mcs->mcs_id;
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event.pcifunc = mcs->pf_map[0];
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for (i = 0; i < MCS_MAX_PAB_INT; i++) {
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if (!(intr & BIT_ULL(i)))
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continue;
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event.intr_mask = (dir == MCS_RX) ?
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MCS_PAB_RX_CHAN_OVERFLOW_INT :
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MCS_PAB_TX_CHAN_OVERFLOW_INT;
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/* Notify the lmac_id info which ran into PAB fatal error */
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event.lmac_id = i;
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mcs_add_intr_wq_entry(mcs, &event);
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}
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}
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