799 lines
19 KiB
C
799 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Marvell RVU Virtual Function ethernet driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#include <linux/etherdevice.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/net_tstamp.h>
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#include "otx2_common.h"
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#include "otx2_reg.h"
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#include "otx2_ptp.h"
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#include "cn10k.h"
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#define DRV_NAME "rvu_nicvf"
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#define DRV_STRING "Marvell RVU NIC Virtual Function Driver"
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static const struct pci_device_id otx2_vf_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) },
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{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) },
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{ }
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};
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MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
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MODULE_DESCRIPTION(DRV_STRING);
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MODULE_LICENSE("GPL v2");
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MODULE_DEVICE_TABLE(pci, otx2_vf_id_table);
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/* RVU VF Interrupt Vector Enumeration */
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enum {
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RVU_VF_INT_VEC_MBOX = 0x0,
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};
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static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf,
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struct mbox_msghdr *msg)
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{
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if (msg->id >= MBOX_MSG_MAX) {
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dev_err(vf->dev,
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"Mbox msg with unknown ID %d\n", msg->id);
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return;
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}
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if (msg->sig != OTX2_MBOX_RSP_SIG) {
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dev_err(vf->dev,
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"Mbox msg with wrong signature %x, ID %d\n",
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msg->sig, msg->id);
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return;
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}
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if (msg->rc == MBOX_MSG_INVALID) {
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dev_err(vf->dev,
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"PF/AF says the sent msg(s) %d were invalid\n",
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msg->id);
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return;
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}
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switch (msg->id) {
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case MBOX_MSG_READY:
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vf->pcifunc = msg->pcifunc;
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break;
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case MBOX_MSG_MSIX_OFFSET:
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mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg);
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break;
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case MBOX_MSG_NPA_LF_ALLOC:
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mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg);
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break;
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case MBOX_MSG_NIX_LF_ALLOC:
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mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg);
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break;
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case MBOX_MSG_NIX_TXSCH_ALLOC:
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mbox_handler_nix_txsch_alloc(vf,
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(struct nix_txsch_alloc_rsp *)msg);
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break;
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case MBOX_MSG_NIX_BP_ENABLE:
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mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg);
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break;
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default:
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if (msg->rc)
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dev_err(vf->dev,
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"Mbox msg response has err %d, ID %d\n",
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msg->rc, msg->id);
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}
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}
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static void otx2vf_vfaf_mbox_handler(struct work_struct *work)
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{
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struct otx2_mbox_dev *mdev;
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struct mbox_hdr *rsp_hdr;
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struct mbox_msghdr *msg;
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struct otx2_mbox *mbox;
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struct mbox *af_mbox;
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int offset, id;
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af_mbox = container_of(work, struct mbox, mbox_wrk);
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mbox = &af_mbox->mbox;
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mdev = &mbox->dev[0];
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rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
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if (af_mbox->num_msgs == 0)
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return;
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offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
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for (id = 0; id < af_mbox->num_msgs; id++) {
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msg = (struct mbox_msghdr *)(mdev->mbase + offset);
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otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg);
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offset = mbox->rx_start + msg->next_msgoff;
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if (mdev->msgs_acked == (af_mbox->num_msgs - 1))
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__otx2_mbox_reset(mbox, 0);
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mdev->msgs_acked++;
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}
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}
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static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf,
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struct mbox_msghdr *req)
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{
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struct msg_rsp *rsp;
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int err;
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/* Check if valid, if not reply with a invalid msg */
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if (req->sig != OTX2_MBOX_REQ_SIG) {
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otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id);
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return -ENODEV;
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}
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switch (req->id) {
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case MBOX_MSG_CGX_LINK_EVENT:
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rsp = (struct msg_rsp *)otx2_mbox_alloc_msg(
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&vf->mbox.mbox_up, 0,
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sizeof(struct msg_rsp));
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if (!rsp)
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return -ENOMEM;
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rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
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rsp->hdr.sig = OTX2_MBOX_RSP_SIG;
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rsp->hdr.pcifunc = 0;
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rsp->hdr.rc = 0;
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err = otx2_mbox_up_handler_cgx_link_event(
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vf, (struct cgx_link_info_msg *)req, rsp);
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return err;
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default:
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otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id);
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return -ENODEV;
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}
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return 0;
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}
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static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work)
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{
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struct otx2_mbox_dev *mdev;
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struct mbox_hdr *rsp_hdr;
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struct mbox_msghdr *msg;
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struct otx2_mbox *mbox;
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struct mbox *vf_mbox;
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struct otx2_nic *vf;
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int offset, id;
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vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
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vf = vf_mbox->pfvf;
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mbox = &vf_mbox->mbox_up;
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mdev = &mbox->dev[0];
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rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
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if (vf_mbox->up_num_msgs == 0)
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return;
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offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
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for (id = 0; id < vf_mbox->up_num_msgs; id++) {
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msg = (struct mbox_msghdr *)(mdev->mbase + offset);
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otx2vf_process_mbox_msg_up(vf, msg);
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offset = mbox->rx_start + msg->next_msgoff;
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}
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otx2_mbox_msg_send(mbox, 0);
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}
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static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq)
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{
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struct otx2_nic *vf = (struct otx2_nic *)vf_irq;
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struct otx2_mbox_dev *mdev;
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struct otx2_mbox *mbox;
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struct mbox_hdr *hdr;
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/* Clear the IRQ */
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otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
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/* Read latest mbox data */
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smp_rmb();
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/* Check for PF => VF response messages */
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mbox = &vf->mbox.mbox;
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mdev = &mbox->dev[0];
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otx2_sync_mbox_bbuf(mbox, 0);
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trace_otx2_msg_interrupt(mbox->pdev, "PF to VF", BIT_ULL(0));
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hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
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if (hdr->num_msgs) {
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vf->mbox.num_msgs = hdr->num_msgs;
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hdr->num_msgs = 0;
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memset(mbox->hwbase + mbox->rx_start, 0,
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ALIGN(sizeof(struct mbox_hdr), sizeof(u64)));
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queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk);
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}
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/* Check for PF => VF notification messages */
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mbox = &vf->mbox.mbox_up;
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mdev = &mbox->dev[0];
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otx2_sync_mbox_bbuf(mbox, 0);
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hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
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if (hdr->num_msgs) {
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vf->mbox.up_num_msgs = hdr->num_msgs;
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hdr->num_msgs = 0;
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memset(mbox->hwbase + mbox->rx_start, 0,
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ALIGN(sizeof(struct mbox_hdr), sizeof(u64)));
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queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk);
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}
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return IRQ_HANDLED;
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}
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static void otx2vf_disable_mbox_intr(struct otx2_nic *vf)
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{
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int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX);
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/* Disable VF => PF mailbox IRQ */
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otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0));
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free_irq(vector, vf);
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}
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static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf)
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{
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struct otx2_hw *hw = &vf->hw;
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struct msg_req *req;
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char *irq_name;
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int err;
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/* Register mailbox interrupt handler */
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irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE];
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snprintf(irq_name, NAME_SIZE, "RVUVFAF Mbox");
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err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX),
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otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf);
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if (err) {
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dev_err(vf->dev,
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"RVUPF: IRQ registration failed for VFAF mbox irq\n");
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return err;
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}
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/* Enable mailbox interrupt for msgs coming from PF.
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* First clear to avoid spurious interrupts, if any.
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*/
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otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
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otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0));
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if (!probe_pf)
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return 0;
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/* Check mailbox communication with PF */
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req = otx2_mbox_alloc_msg_ready(&vf->mbox);
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if (!req) {
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otx2vf_disable_mbox_intr(vf);
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return -ENOMEM;
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}
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err = otx2_sync_mbox_msg(&vf->mbox);
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if (err) {
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dev_warn(vf->dev,
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"AF not responding to mailbox, deferring probe\n");
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otx2vf_disable_mbox_intr(vf);
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return -EPROBE_DEFER;
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}
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return 0;
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}
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static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf)
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{
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struct mbox *mbox = &vf->mbox;
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if (vf->mbox_wq) {
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destroy_workqueue(vf->mbox_wq);
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vf->mbox_wq = NULL;
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}
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if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
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iounmap((void __iomem *)mbox->mbox.hwbase);
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otx2_mbox_destroy(&mbox->mbox);
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otx2_mbox_destroy(&mbox->mbox_up);
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}
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static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf)
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{
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struct mbox *mbox = &vf->mbox;
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void __iomem *hwbase;
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int err;
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mbox->pfvf = vf;
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vf->mbox_wq = alloc_workqueue("otx2_vfaf_mailbox",
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WQ_UNBOUND | WQ_HIGHPRI |
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WQ_MEM_RECLAIM, 1);
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if (!vf->mbox_wq)
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return -ENOMEM;
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if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) {
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/* For cn10k platform, VF mailbox region is in its BAR2
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* register space
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*/
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hwbase = vf->reg_base + RVU_VF_MBOX_REGION;
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} else {
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/* Mailbox is a reserved memory (in RAM) region shared between
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* admin function (i.e PF0) and this VF, shouldn't be mapped as
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* device memory to allow unaligned accesses.
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*/
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hwbase = ioremap_wc(pci_resource_start(vf->pdev,
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PCI_MBOX_BAR_NUM),
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pci_resource_len(vf->pdev,
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PCI_MBOX_BAR_NUM));
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if (!hwbase) {
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dev_err(vf->dev, "Unable to map VFAF mailbox region\n");
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err = -ENOMEM;
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goto exit;
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}
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}
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err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base,
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MBOX_DIR_VFPF, 1);
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if (err)
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goto exit;
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err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base,
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MBOX_DIR_VFPF_UP, 1);
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if (err)
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goto exit;
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err = otx2_mbox_bbuf_init(mbox, vf->pdev);
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if (err)
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goto exit;
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INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler);
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INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler);
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mutex_init(&mbox->lock);
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return 0;
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exit:
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if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
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iounmap(hwbase);
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destroy_workqueue(vf->mbox_wq);
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return err;
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}
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static int otx2vf_open(struct net_device *netdev)
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{
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struct otx2_nic *vf;
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int err;
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err = otx2_open(netdev);
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if (err)
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return err;
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/* LBKs do not receive link events so tell everyone we are up here */
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vf = netdev_priv(netdev);
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if (is_otx2_lbkvf(vf->pdev)) {
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pr_info("%s NIC Link is UP\n", netdev->name);
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netif_carrier_on(netdev);
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netif_tx_start_all_queues(netdev);
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}
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return 0;
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}
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static int otx2vf_stop(struct net_device *netdev)
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{
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return otx2_stop(netdev);
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}
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static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev)
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{
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struct otx2_nic *vf = netdev_priv(netdev);
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int qidx = skb_get_queue_mapping(skb);
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struct otx2_snd_queue *sq;
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struct netdev_queue *txq;
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sq = &vf->qset.sq[qidx];
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txq = netdev_get_tx_queue(netdev, qidx);
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if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) {
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netif_tx_stop_queue(txq);
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/* Check again, incase SQBs got freed up */
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smp_mb();
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if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
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> sq->sqe_thresh)
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netif_tx_wake_queue(txq);
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return NETDEV_TX_BUSY;
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}
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return NETDEV_TX_OK;
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}
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static void otx2vf_set_rx_mode(struct net_device *netdev)
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{
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struct otx2_nic *vf = netdev_priv(netdev);
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queue_work(vf->otx2_wq, &vf->rx_mode_work);
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}
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static void otx2vf_do_set_rx_mode(struct work_struct *work)
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{
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struct otx2_nic *vf = container_of(work, struct otx2_nic, rx_mode_work);
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struct net_device *netdev = vf->netdev;
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unsigned int flags = netdev->flags;
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struct nix_rx_mode *req;
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mutex_lock(&vf->mbox.lock);
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req = otx2_mbox_alloc_msg_nix_set_rx_mode(&vf->mbox);
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if (!req) {
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mutex_unlock(&vf->mbox.lock);
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return;
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}
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req->mode = NIX_RX_MODE_UCAST;
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if (flags & IFF_PROMISC)
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req->mode |= NIX_RX_MODE_PROMISC;
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if (flags & (IFF_ALLMULTI | IFF_MULTICAST))
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req->mode |= NIX_RX_MODE_ALLMULTI;
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req->mode |= NIX_RX_MODE_USE_MCE;
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otx2_sync_mbox_msg(&vf->mbox);
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mutex_unlock(&vf->mbox.lock);
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}
|
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|
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static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu)
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{
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bool if_up = netif_running(netdev);
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int err = 0;
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|
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if (if_up)
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otx2vf_stop(netdev);
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netdev_info(netdev, "Changing MTU from %d to %d\n",
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netdev->mtu, new_mtu);
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netdev->mtu = new_mtu;
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if (if_up)
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err = otx2vf_open(netdev);
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return err;
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}
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|
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static void otx2vf_reset_task(struct work_struct *work)
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{
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struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task);
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|
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rtnl_lock();
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|
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if (netif_running(vf->netdev)) {
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otx2vf_stop(vf->netdev);
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vf->reset_count++;
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otx2vf_open(vf->netdev);
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}
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|
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rtnl_unlock();
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}
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|
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static int otx2vf_set_features(struct net_device *netdev,
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netdev_features_t features)
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{
|
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return otx2_handle_ntuple_tc_features(netdev, features);
|
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}
|
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|
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static const struct net_device_ops otx2vf_netdev_ops = {
|
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.ndo_open = otx2vf_open,
|
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.ndo_stop = otx2vf_stop,
|
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.ndo_start_xmit = otx2vf_xmit,
|
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.ndo_set_rx_mode = otx2vf_set_rx_mode,
|
|
.ndo_set_mac_address = otx2_set_mac_address,
|
|
.ndo_change_mtu = otx2vf_change_mtu,
|
|
.ndo_set_features = otx2vf_set_features,
|
|
.ndo_get_stats64 = otx2_get_stats64,
|
|
.ndo_tx_timeout = otx2_tx_timeout,
|
|
.ndo_eth_ioctl = otx2_ioctl,
|
|
.ndo_setup_tc = otx2_setup_tc,
|
|
};
|
|
|
|
static int otx2_wq_init(struct otx2_nic *vf)
|
|
{
|
|
vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq");
|
|
if (!vf->otx2_wq)
|
|
return -ENOMEM;
|
|
|
|
INIT_WORK(&vf->rx_mode_work, otx2vf_do_set_rx_mode);
|
|
INIT_WORK(&vf->reset_task, otx2vf_reset_task);
|
|
return 0;
|
|
}
|
|
|
|
static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf)
|
|
{
|
|
struct otx2_hw *hw = &vf->hw;
|
|
int num_vec, err;
|
|
|
|
num_vec = hw->nix_msixoff;
|
|
num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
|
|
|
|
otx2vf_disable_mbox_intr(vf);
|
|
pci_free_irq_vectors(hw->pdev);
|
|
err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
|
|
if (err < 0) {
|
|
dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n",
|
|
__func__, num_vec);
|
|
return err;
|
|
}
|
|
|
|
return otx2vf_register_mbox_intr(vf, false);
|
|
}
|
|
|
|
static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
int num_vec = pci_msix_vec_count(pdev);
|
|
struct device *dev = &pdev->dev;
|
|
struct net_device *netdev;
|
|
struct otx2_nic *vf;
|
|
struct otx2_hw *hw;
|
|
int err, qcount;
|
|
|
|
err = pcim_enable_device(pdev);
|
|
if (err) {
|
|
dev_err(dev, "Failed to enable PCI device\n");
|
|
return err;
|
|
}
|
|
|
|
err = pci_request_regions(pdev, DRV_NAME);
|
|
if (err) {
|
|
dev_err(dev, "PCI request regions failed 0x%x\n", err);
|
|
return err;
|
|
}
|
|
|
|
err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
|
|
if (err) {
|
|
dev_err(dev, "DMA mask config failed, abort\n");
|
|
goto err_release_regions;
|
|
}
|
|
|
|
pci_set_master(pdev);
|
|
|
|
qcount = num_online_cpus();
|
|
netdev = alloc_etherdev_mqs(sizeof(*vf), qcount, qcount);
|
|
if (!netdev) {
|
|
err = -ENOMEM;
|
|
goto err_release_regions;
|
|
}
|
|
|
|
pci_set_drvdata(pdev, netdev);
|
|
SET_NETDEV_DEV(netdev, &pdev->dev);
|
|
vf = netdev_priv(netdev);
|
|
vf->netdev = netdev;
|
|
vf->pdev = pdev;
|
|
vf->dev = dev;
|
|
vf->iommu_domain = iommu_get_domain_for_dev(dev);
|
|
|
|
vf->flags |= OTX2_FLAG_INTF_DOWN;
|
|
hw = &vf->hw;
|
|
hw->pdev = vf->pdev;
|
|
hw->rx_queues = qcount;
|
|
hw->tx_queues = qcount;
|
|
hw->max_queues = qcount;
|
|
hw->tot_tx_queues = qcount;
|
|
hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN;
|
|
/* Use CQE of 128 byte descriptor size by default */
|
|
hw->xqe_size = 128;
|
|
|
|
hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
|
|
GFP_KERNEL);
|
|
if (!hw->irq_name) {
|
|
err = -ENOMEM;
|
|
goto err_free_netdev;
|
|
}
|
|
|
|
hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
|
|
sizeof(cpumask_var_t), GFP_KERNEL);
|
|
if (!hw->affinity_mask) {
|
|
err = -ENOMEM;
|
|
goto err_free_netdev;
|
|
}
|
|
|
|
err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
|
|
if (err < 0) {
|
|
dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
|
|
__func__, num_vec);
|
|
goto err_free_netdev;
|
|
}
|
|
|
|
vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
|
|
if (!vf->reg_base) {
|
|
dev_err(dev, "Unable to map physical function CSRs, aborting\n");
|
|
err = -ENOMEM;
|
|
goto err_free_irq_vectors;
|
|
}
|
|
|
|
otx2_setup_dev_hw_settings(vf);
|
|
/* Init VF <=> PF mailbox stuff */
|
|
err = otx2vf_vfaf_mbox_init(vf);
|
|
if (err)
|
|
goto err_free_irq_vectors;
|
|
|
|
/* Register mailbox interrupt */
|
|
err = otx2vf_register_mbox_intr(vf, true);
|
|
if (err)
|
|
goto err_mbox_destroy;
|
|
|
|
/* Request AF to attach NPA and LIX LFs to this AF */
|
|
err = otx2_attach_npa_nix(vf);
|
|
if (err)
|
|
goto err_disable_mbox_intr;
|
|
|
|
err = otx2vf_realloc_msix_vectors(vf);
|
|
if (err)
|
|
goto err_detach_rsrc;
|
|
|
|
err = otx2_set_real_num_queues(netdev, qcount, qcount);
|
|
if (err)
|
|
goto err_detach_rsrc;
|
|
|
|
err = cn10k_lmtst_init(vf);
|
|
if (err)
|
|
goto err_detach_rsrc;
|
|
|
|
/* Don't check for error. Proceed without ptp */
|
|
otx2_ptp_init(vf);
|
|
|
|
/* Assign default mac address */
|
|
otx2_get_mac_from_af(netdev);
|
|
|
|
netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
|
|
NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
|
|
NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
|
|
NETIF_F_GSO_UDP_L4;
|
|
netdev->features = netdev->hw_features;
|
|
/* Support TSO on tag interface */
|
|
netdev->vlan_features |= netdev->features;
|
|
netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
|
|
NETIF_F_HW_VLAN_STAG_TX;
|
|
netdev->features |= netdev->hw_features;
|
|
|
|
netdev->hw_features |= NETIF_F_NTUPLE;
|
|
netdev->hw_features |= NETIF_F_RXALL;
|
|
netdev->hw_features |= NETIF_F_HW_TC;
|
|
|
|
netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS);
|
|
netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
|
|
|
|
netdev->netdev_ops = &otx2vf_netdev_ops;
|
|
|
|
netdev->min_mtu = OTX2_MIN_MTU;
|
|
netdev->max_mtu = otx2_get_max_mtu(vf);
|
|
|
|
/* To distinguish, for LBK VFs set netdev name explicitly */
|
|
if (is_otx2_lbkvf(vf->pdev)) {
|
|
int n;
|
|
|
|
n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK;
|
|
/* Need to subtract 1 to get proper VF number */
|
|
n -= 1;
|
|
snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n);
|
|
}
|
|
|
|
err = register_netdev(netdev);
|
|
if (err) {
|
|
dev_err(dev, "Failed to register netdevice\n");
|
|
goto err_ptp_destroy;
|
|
}
|
|
|
|
err = otx2_wq_init(vf);
|
|
if (err)
|
|
goto err_unreg_netdev;
|
|
|
|
otx2vf_set_ethtool_ops(netdev);
|
|
|
|
err = otx2vf_mcam_flow_init(vf);
|
|
if (err)
|
|
goto err_unreg_netdev;
|
|
|
|
err = otx2_init_tc(vf);
|
|
if (err)
|
|
goto err_unreg_netdev;
|
|
|
|
err = otx2_register_dl(vf);
|
|
if (err)
|
|
goto err_shutdown_tc;
|
|
|
|
#ifdef CONFIG_DCB
|
|
err = otx2_dcbnl_set_ops(netdev);
|
|
if (err)
|
|
goto err_shutdown_tc;
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
err_shutdown_tc:
|
|
otx2_shutdown_tc(vf);
|
|
err_unreg_netdev:
|
|
unregister_netdev(netdev);
|
|
err_ptp_destroy:
|
|
otx2_ptp_destroy(vf);
|
|
err_detach_rsrc:
|
|
free_percpu(vf->hw.lmt_info);
|
|
if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
|
|
qmem_free(vf->dev, vf->dync_lmt);
|
|
otx2_detach_resources(&vf->mbox);
|
|
err_disable_mbox_intr:
|
|
otx2vf_disable_mbox_intr(vf);
|
|
err_mbox_destroy:
|
|
otx2vf_vfaf_mbox_destroy(vf);
|
|
err_free_irq_vectors:
|
|
pci_free_irq_vectors(hw->pdev);
|
|
err_free_netdev:
|
|
pci_set_drvdata(pdev, NULL);
|
|
free_netdev(netdev);
|
|
err_release_regions:
|
|
pci_release_regions(pdev);
|
|
return err;
|
|
}
|
|
|
|
static void otx2vf_remove(struct pci_dev *pdev)
|
|
{
|
|
struct net_device *netdev = pci_get_drvdata(pdev);
|
|
struct otx2_nic *vf;
|
|
|
|
if (!netdev)
|
|
return;
|
|
|
|
vf = netdev_priv(netdev);
|
|
|
|
/* Disable 802.3x pause frames */
|
|
if (vf->flags & OTX2_FLAG_RX_PAUSE_ENABLED ||
|
|
(vf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) {
|
|
vf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED;
|
|
vf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED;
|
|
otx2_config_pause_frm(vf);
|
|
}
|
|
|
|
#ifdef CONFIG_DCB
|
|
/* Disable PFC config */
|
|
if (vf->pfc_en) {
|
|
vf->pfc_en = 0;
|
|
otx2_config_priority_flow_ctrl(vf);
|
|
}
|
|
#endif
|
|
|
|
cancel_work_sync(&vf->reset_task);
|
|
otx2_unregister_dl(vf);
|
|
unregister_netdev(netdev);
|
|
if (vf->otx2_wq)
|
|
destroy_workqueue(vf->otx2_wq);
|
|
otx2_ptp_destroy(vf);
|
|
otx2_mcam_flow_del(vf);
|
|
otx2_shutdown_tc(vf);
|
|
otx2vf_disable_mbox_intr(vf);
|
|
otx2_detach_resources(&vf->mbox);
|
|
free_percpu(vf->hw.lmt_info);
|
|
if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
|
|
qmem_free(vf->dev, vf->dync_lmt);
|
|
otx2vf_vfaf_mbox_destroy(vf);
|
|
pci_free_irq_vectors(vf->pdev);
|
|
pci_set_drvdata(pdev, NULL);
|
|
free_netdev(netdev);
|
|
|
|
pci_release_regions(pdev);
|
|
}
|
|
|
|
static struct pci_driver otx2vf_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = otx2_vf_id_table,
|
|
.probe = otx2vf_probe,
|
|
.remove = otx2vf_remove,
|
|
.shutdown = otx2vf_remove,
|
|
};
|
|
|
|
static int __init otx2vf_init_module(void)
|
|
{
|
|
pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
|
|
|
|
return pci_register_driver(&otx2vf_driver);
|
|
}
|
|
|
|
static void __exit otx2vf_cleanup_module(void)
|
|
{
|
|
pci_unregister_driver(&otx2vf_driver);
|
|
}
|
|
|
|
module_init(otx2vf_init_module);
|
|
module_exit(otx2vf_cleanup_module);
|