516 lines
14 KiB
C
516 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
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/* Gigabit Ethernet driver for Mellanox BlueField SoC
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*
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* Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
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*/
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#include <linux/acpi.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/etherdevice.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/skbuff.h>
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#include "mlxbf_gige.h"
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#include "mlxbf_gige_regs.h"
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/* Allocate SKB whose payload pointer aligns with the Bluefield
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* hardware DMA limitation, i.e. DMA operation can't cross
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* a 4KB boundary. A maximum packet size of 2KB is assumed in the
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* alignment formula. The alignment logic overallocates an SKB,
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* and then adjusts the headroom so that the SKB data pointer is
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* naturally aligned to a 2KB boundary.
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*/
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struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv,
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unsigned int map_len,
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dma_addr_t *buf_dma,
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enum dma_data_direction dir)
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{
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struct sk_buff *skb;
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u64 addr, offset;
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/* Overallocate the SKB so that any headroom adjustment (to
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* provide 2KB natural alignment) does not exceed payload area
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*/
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skb = netdev_alloc_skb(priv->netdev, MLXBF_GIGE_DEFAULT_BUF_SZ * 2);
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if (!skb)
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return NULL;
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/* Adjust the headroom so that skb->data is naturally aligned to
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* a 2KB boundary, which is the maximum packet size supported.
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*/
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addr = (long)skb->data;
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offset = (addr + MLXBF_GIGE_DEFAULT_BUF_SZ - 1) &
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~(MLXBF_GIGE_DEFAULT_BUF_SZ - 1);
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offset -= addr;
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if (offset)
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skb_reserve(skb, offset);
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/* Return streaming DMA mapping to caller */
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*buf_dma = dma_map_single(priv->dev, skb->data, map_len, dir);
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if (dma_mapping_error(priv->dev, *buf_dma)) {
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dev_kfree_skb(skb);
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*buf_dma = (dma_addr_t)0;
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return NULL;
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}
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return skb;
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}
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static void mlxbf_gige_initial_mac(struct mlxbf_gige *priv)
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{
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u8 mac[ETH_ALEN];
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u64 local_mac;
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eth_zero_addr(mac);
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mlxbf_gige_get_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,
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&local_mac);
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u64_to_ether_addr(local_mac, mac);
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if (is_valid_ether_addr(mac)) {
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eth_hw_addr_set(priv->netdev, mac);
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} else {
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/* Provide a random MAC if for some reason the device has
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* not been configured with a valid MAC address already.
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*/
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eth_hw_addr_random(priv->netdev);
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}
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local_mac = ether_addr_to_u64(priv->netdev->dev_addr);
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mlxbf_gige_set_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,
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local_mac);
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}
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static void mlxbf_gige_cache_stats(struct mlxbf_gige *priv)
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{
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struct mlxbf_gige_stats *p;
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/* Cache stats that will be cleared by clean port operation */
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p = &priv->stats;
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p->rx_din_dropped_pkts += readq(priv->base +
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MLXBF_GIGE_RX_DIN_DROP_COUNTER);
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p->rx_filter_passed_pkts += readq(priv->base +
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MLXBF_GIGE_RX_PASS_COUNTER_ALL);
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p->rx_filter_discard_pkts += readq(priv->base +
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MLXBF_GIGE_RX_DISC_COUNTER_ALL);
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}
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static int mlxbf_gige_clean_port(struct mlxbf_gige *priv)
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{
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u64 control;
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u64 temp;
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int err;
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/* Set the CLEAN_PORT_EN bit to trigger SW reset */
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control = readq(priv->base + MLXBF_GIGE_CONTROL);
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control |= MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;
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writeq(control, priv->base + MLXBF_GIGE_CONTROL);
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/* Ensure completion of "clean port" write before polling status */
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mb();
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err = readq_poll_timeout_atomic(priv->base + MLXBF_GIGE_STATUS, temp,
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(temp & MLXBF_GIGE_STATUS_READY),
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100, 100000);
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/* Clear the CLEAN_PORT_EN bit at end of this loop */
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control = readq(priv->base + MLXBF_GIGE_CONTROL);
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control &= ~MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;
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writeq(control, priv->base + MLXBF_GIGE_CONTROL);
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return err;
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}
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static int mlxbf_gige_open(struct net_device *netdev)
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{
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struct mlxbf_gige *priv = netdev_priv(netdev);
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struct phy_device *phydev = netdev->phydev;
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u64 int_en;
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int err;
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err = mlxbf_gige_request_irqs(priv);
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if (err)
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return err;
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mlxbf_gige_cache_stats(priv);
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err = mlxbf_gige_clean_port(priv);
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if (err)
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goto free_irqs;
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/* Clear driver's valid_polarity to match hardware,
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* since the above call to clean_port() resets the
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* receive polarity used by hardware.
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*/
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priv->valid_polarity = 0;
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err = mlxbf_gige_rx_init(priv);
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if (err)
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goto free_irqs;
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err = mlxbf_gige_tx_init(priv);
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if (err)
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goto rx_deinit;
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phy_start(phydev);
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netif_napi_add(netdev, &priv->napi, mlxbf_gige_poll);
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napi_enable(&priv->napi);
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netif_start_queue(netdev);
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/* Set bits in INT_EN that we care about */
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int_en = MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR |
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MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS |
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MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE |
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MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE |
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MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR |
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MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR |
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MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET;
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/* Ensure completion of all initialization before enabling interrupts */
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mb();
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writeq(int_en, priv->base + MLXBF_GIGE_INT_EN);
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return 0;
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rx_deinit:
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mlxbf_gige_rx_deinit(priv);
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free_irqs:
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mlxbf_gige_free_irqs(priv);
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return err;
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}
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static int mlxbf_gige_stop(struct net_device *netdev)
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{
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struct mlxbf_gige *priv = netdev_priv(netdev);
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writeq(0, priv->base + MLXBF_GIGE_INT_EN);
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netif_stop_queue(netdev);
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napi_disable(&priv->napi);
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netif_napi_del(&priv->napi);
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mlxbf_gige_free_irqs(priv);
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phy_stop(netdev->phydev);
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mlxbf_gige_rx_deinit(priv);
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mlxbf_gige_tx_deinit(priv);
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mlxbf_gige_cache_stats(priv);
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mlxbf_gige_clean_port(priv);
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return 0;
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}
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static int mlxbf_gige_eth_ioctl(struct net_device *netdev,
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struct ifreq *ifr, int cmd)
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{
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if (!(netif_running(netdev)))
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return -EINVAL;
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return phy_mii_ioctl(netdev->phydev, ifr, cmd);
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}
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static void mlxbf_gige_set_rx_mode(struct net_device *netdev)
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{
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struct mlxbf_gige *priv = netdev_priv(netdev);
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bool new_promisc_enabled;
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new_promisc_enabled = netdev->flags & IFF_PROMISC;
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/* Only write to the hardware registers if the new setting
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* of promiscuous mode is different from the current one.
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*/
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if (new_promisc_enabled != priv->promisc_enabled) {
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priv->promisc_enabled = new_promisc_enabled;
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if (new_promisc_enabled)
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mlxbf_gige_enable_promisc(priv);
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else
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mlxbf_gige_disable_promisc(priv);
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}
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}
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static void mlxbf_gige_get_stats64(struct net_device *netdev,
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struct rtnl_link_stats64 *stats)
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{
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struct mlxbf_gige *priv = netdev_priv(netdev);
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netdev_stats_to_stats64(stats, &netdev->stats);
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stats->rx_length_errors = priv->stats.rx_truncate_errors;
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stats->rx_fifo_errors = priv->stats.rx_din_dropped_pkts +
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readq(priv->base + MLXBF_GIGE_RX_DIN_DROP_COUNTER);
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stats->rx_crc_errors = priv->stats.rx_mac_errors;
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stats->rx_errors = stats->rx_length_errors +
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stats->rx_fifo_errors +
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stats->rx_crc_errors;
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stats->tx_fifo_errors = priv->stats.tx_fifo_full;
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stats->tx_errors = stats->tx_fifo_errors;
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}
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static const struct net_device_ops mlxbf_gige_netdev_ops = {
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.ndo_open = mlxbf_gige_open,
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.ndo_stop = mlxbf_gige_stop,
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.ndo_start_xmit = mlxbf_gige_start_xmit,
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.ndo_set_mac_address = eth_mac_addr,
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.ndo_validate_addr = eth_validate_addr,
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.ndo_eth_ioctl = mlxbf_gige_eth_ioctl,
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.ndo_set_rx_mode = mlxbf_gige_set_rx_mode,
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.ndo_get_stats64 = mlxbf_gige_get_stats64,
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};
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static void mlxbf_gige_bf2_adjust_link(struct net_device *netdev)
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{
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struct phy_device *phydev = netdev->phydev;
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phy_print_status(phydev);
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}
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static void mlxbf_gige_bf3_adjust_link(struct net_device *netdev)
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{
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struct mlxbf_gige *priv = netdev_priv(netdev);
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struct phy_device *phydev = netdev->phydev;
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u8 sgmii_mode;
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u16 ipg_size;
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u32 val;
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if (phydev->link && phydev->speed != priv->prev_speed) {
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switch (phydev->speed) {
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case 1000:
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ipg_size = MLXBF_GIGE_1G_IPG_SIZE;
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sgmii_mode = MLXBF_GIGE_1G_SGMII_MODE;
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break;
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case 100:
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ipg_size = MLXBF_GIGE_100M_IPG_SIZE;
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sgmii_mode = MLXBF_GIGE_100M_SGMII_MODE;
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break;
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case 10:
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ipg_size = MLXBF_GIGE_10M_IPG_SIZE;
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sgmii_mode = MLXBF_GIGE_10M_SGMII_MODE;
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break;
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default:
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return;
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}
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val = readl(priv->plu_base + MLXBF_GIGE_PLU_TX_REG0);
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val &= ~(MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK | MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK);
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val |= FIELD_PREP(MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK, ipg_size);
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val |= FIELD_PREP(MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK, sgmii_mode);
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writel(val, priv->plu_base + MLXBF_GIGE_PLU_TX_REG0);
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val = readl(priv->plu_base + MLXBF_GIGE_PLU_RX_REG0);
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val &= ~MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK;
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val |= FIELD_PREP(MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK, sgmii_mode);
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writel(val, priv->plu_base + MLXBF_GIGE_PLU_RX_REG0);
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priv->prev_speed = phydev->speed;
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}
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phy_print_status(phydev);
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}
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static void mlxbf_gige_bf2_set_phy_link_mode(struct phy_device *phydev)
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{
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/* MAC only supports 1000T full duplex mode */
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phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
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phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT);
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phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
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phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
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phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
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/* Only symmetric pause with flow control enabled is supported so no
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* need to negotiate pause.
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*/
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linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising);
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linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising);
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}
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static void mlxbf_gige_bf3_set_phy_link_mode(struct phy_device *phydev)
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{
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/* MAC only supports full duplex mode */
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phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
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phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
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phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
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/* Only symmetric pause with flow control enabled is supported so no
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* need to negotiate pause.
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*/
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linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising);
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linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising);
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}
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static struct mlxbf_gige_link_cfg mlxbf_gige_link_cfgs[] = {
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[MLXBF_GIGE_VERSION_BF2] = {
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.set_phy_link_mode = mlxbf_gige_bf2_set_phy_link_mode,
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.adjust_link = mlxbf_gige_bf2_adjust_link,
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.phy_mode = PHY_INTERFACE_MODE_GMII
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},
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[MLXBF_GIGE_VERSION_BF3] = {
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.set_phy_link_mode = mlxbf_gige_bf3_set_phy_link_mode,
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.adjust_link = mlxbf_gige_bf3_adjust_link,
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.phy_mode = PHY_INTERFACE_MODE_SGMII
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}
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};
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static int mlxbf_gige_probe(struct platform_device *pdev)
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{
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struct phy_device *phydev;
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struct net_device *netdev;
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struct mlxbf_gige *priv;
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void __iomem *llu_base;
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void __iomem *plu_base;
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void __iomem *base;
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int addr, phy_irq;
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u64 control;
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int err;
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base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MAC);
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if (IS_ERR(base))
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return PTR_ERR(base);
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llu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_LLU);
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if (IS_ERR(llu_base))
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return PTR_ERR(llu_base);
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plu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_PLU);
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if (IS_ERR(plu_base))
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return PTR_ERR(plu_base);
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/* Perform general init of GigE block */
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control = readq(base + MLXBF_GIGE_CONTROL);
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control |= MLXBF_GIGE_CONTROL_PORT_EN;
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writeq(control, base + MLXBF_GIGE_CONTROL);
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netdev = devm_alloc_etherdev(&pdev->dev, sizeof(*priv));
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if (!netdev)
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return -ENOMEM;
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SET_NETDEV_DEV(netdev, &pdev->dev);
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netdev->netdev_ops = &mlxbf_gige_netdev_ops;
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netdev->ethtool_ops = &mlxbf_gige_ethtool_ops;
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priv = netdev_priv(netdev);
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priv->netdev = netdev;
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platform_set_drvdata(pdev, priv);
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priv->dev = &pdev->dev;
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priv->pdev = pdev;
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spin_lock_init(&priv->lock);
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priv->hw_version = readq(base + MLXBF_GIGE_VERSION);
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/* Attach MDIO device */
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err = mlxbf_gige_mdio_probe(pdev, priv);
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if (err)
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return err;
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priv->base = base;
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priv->llu_base = llu_base;
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priv->plu_base = plu_base;
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priv->rx_q_entries = MLXBF_GIGE_DEFAULT_RXQ_SZ;
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priv->tx_q_entries = MLXBF_GIGE_DEFAULT_TXQ_SZ;
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/* Write initial MAC address to hardware */
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mlxbf_gige_initial_mac(priv);
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err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
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if (err) {
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dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err);
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goto out;
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}
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priv->error_irq = platform_get_irq(pdev, MLXBF_GIGE_ERROR_INTR_IDX);
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priv->rx_irq = platform_get_irq(pdev, MLXBF_GIGE_RECEIVE_PKT_INTR_IDX);
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priv->llu_plu_irq = platform_get_irq(pdev, MLXBF_GIGE_LLU_PLU_INTR_IDX);
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phy_irq = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(&pdev->dev), "phy-gpios", 0);
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if (phy_irq < 0) {
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dev_err(&pdev->dev, "Error getting PHY irq. Use polling instead");
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phy_irq = PHY_POLL;
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}
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phydev = phy_find_first(priv->mdiobus);
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if (!phydev) {
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err = -ENODEV;
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goto out;
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}
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addr = phydev->mdio.addr;
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priv->mdiobus->irq[addr] = phy_irq;
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phydev->irq = phy_irq;
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err = phy_connect_direct(netdev, phydev,
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mlxbf_gige_link_cfgs[priv->hw_version].adjust_link,
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mlxbf_gige_link_cfgs[priv->hw_version].phy_mode);
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if (err) {
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dev_err(&pdev->dev, "Could not attach to PHY\n");
|
|
goto out;
|
|
}
|
|
|
|
mlxbf_gige_link_cfgs[priv->hw_version].set_phy_link_mode(phydev);
|
|
|
|
/* Display information about attached PHY device */
|
|
phy_attached_info(phydev);
|
|
|
|
err = register_netdev(netdev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Failed to register netdev\n");
|
|
phy_disconnect(phydev);
|
|
goto out;
|
|
}
|
|
|
|
return 0;
|
|
|
|
out:
|
|
mlxbf_gige_mdio_remove(priv);
|
|
return err;
|
|
}
|
|
|
|
static int mlxbf_gige_remove(struct platform_device *pdev)
|
|
{
|
|
struct mlxbf_gige *priv = platform_get_drvdata(pdev);
|
|
|
|
unregister_netdev(priv->netdev);
|
|
phy_disconnect(priv->netdev->phydev);
|
|
mlxbf_gige_mdio_remove(priv);
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mlxbf_gige_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct mlxbf_gige *priv = platform_get_drvdata(pdev);
|
|
|
|
writeq(0, priv->base + MLXBF_GIGE_INT_EN);
|
|
mlxbf_gige_clean_port(priv);
|
|
}
|
|
|
|
static const struct acpi_device_id __maybe_unused mlxbf_gige_acpi_match[] = {
|
|
{ "MLNXBF17", 0 },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, mlxbf_gige_acpi_match);
|
|
|
|
static struct platform_driver mlxbf_gige_driver = {
|
|
.probe = mlxbf_gige_probe,
|
|
.remove = mlxbf_gige_remove,
|
|
.shutdown = mlxbf_gige_shutdown,
|
|
.driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.acpi_match_table = ACPI_PTR(mlxbf_gige_acpi_match),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mlxbf_gige_driver);
|
|
|
|
MODULE_DESCRIPTION("Mellanox BlueField SoC Gigabit Ethernet Driver");
|
|
MODULE_AUTHOR("David Thompson <davthompson@nvidia.com>");
|
|
MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
|
|
MODULE_LICENSE("Dual BSD/GPL");
|