1128 lines
29 KiB
C
1128 lines
29 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Microchip ENCX24J600 ethernet driver
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*
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* Copyright (C) 2015 Gridpoint
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* Author: Jon Ringle <jringle@gridpoint.com>
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*/
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/regmap.h>
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#include <linux/skbuff.h>
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#include <linux/spi/spi.h>
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#include "encx24j600_hw.h"
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#define DRV_NAME "encx24j600"
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#define DRV_VERSION "1.0"
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#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
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static int debug = -1;
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module_param(debug, int, 0000);
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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
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/* SRAM memory layout:
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*
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* 0x0000-0x05ff TX buffers 1.5KB (1*1536) reside in the GP area in SRAM
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* 0x0600-0x5fff RX buffers 22.5KB (15*1536) reside in the RX area in SRAM
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*/
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#define ENC_TX_BUF_START 0x0000U
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#define ENC_RX_BUF_START 0x0600U
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#define ENC_RX_BUF_END 0x5fffU
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#define ENC_SRAM_SIZE 0x6000U
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enum {
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RXFILTER_NORMAL,
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RXFILTER_MULTI,
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RXFILTER_PROMISC
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};
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struct encx24j600_priv {
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struct net_device *ndev;
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struct mutex lock; /* device access lock */
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struct encx24j600_context ctx;
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struct sk_buff *tx_skb;
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struct task_struct *kworker_task;
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struct kthread_worker kworker;
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struct kthread_work tx_work;
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struct kthread_work setrx_work;
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u16 next_packet;
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bool hw_enabled;
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bool full_duplex;
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bool autoneg;
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u16 speed;
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int rxfilter;
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u32 msg_enable;
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};
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static void dump_packet(const char *msg, int len, const char *data)
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{
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pr_debug(DRV_NAME ": %s - packet len:%d\n", msg, len);
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print_hex_dump_bytes("pk data: ", DUMP_PREFIX_OFFSET, data, len);
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}
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static void encx24j600_dump_rsv(struct encx24j600_priv *priv, const char *msg,
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struct rsv *rsv)
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{
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struct net_device *dev = priv->ndev;
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netdev_info(dev, "RX packet Len:%d\n", rsv->len);
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netdev_dbg(dev, "%s - NextPk: 0x%04x\n", msg,
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rsv->next_packet);
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netdev_dbg(dev, "RxOK: %d, DribbleNibble: %d\n",
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RSV_GETBIT(rsv->rxstat, RSV_RXOK),
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RSV_GETBIT(rsv->rxstat, RSV_DRIBBLENIBBLE));
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netdev_dbg(dev, "CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
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RSV_GETBIT(rsv->rxstat, RSV_CRCERROR),
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RSV_GETBIT(rsv->rxstat, RSV_LENCHECKERR),
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RSV_GETBIT(rsv->rxstat, RSV_LENOUTOFRANGE));
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netdev_dbg(dev, "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n",
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RSV_GETBIT(rsv->rxstat, RSV_RXMULTICAST),
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RSV_GETBIT(rsv->rxstat, RSV_RXBROADCAST),
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RSV_GETBIT(rsv->rxstat, RSV_RXLONGEVDROPEV),
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RSV_GETBIT(rsv->rxstat, RSV_CARRIEREV));
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netdev_dbg(dev, "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n",
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RSV_GETBIT(rsv->rxstat, RSV_RXCONTROLFRAME),
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RSV_GETBIT(rsv->rxstat, RSV_RXPAUSEFRAME),
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RSV_GETBIT(rsv->rxstat, RSV_RXUNKNOWNOPCODE),
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RSV_GETBIT(rsv->rxstat, RSV_RXTYPEVLAN));
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}
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static u16 encx24j600_read_reg(struct encx24j600_priv *priv, u8 reg)
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{
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struct net_device *dev = priv->ndev;
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unsigned int val = 0;
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int ret = regmap_read(priv->ctx.regmap, reg, &val);
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if (unlikely(ret))
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netif_err(priv, drv, dev, "%s: error %d reading reg %02x\n",
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__func__, ret, reg);
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return val;
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}
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static void encx24j600_write_reg(struct encx24j600_priv *priv, u8 reg, u16 val)
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{
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struct net_device *dev = priv->ndev;
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int ret = regmap_write(priv->ctx.regmap, reg, val);
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if (unlikely(ret))
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netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
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__func__, ret, reg, val);
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}
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static void encx24j600_update_reg(struct encx24j600_priv *priv, u8 reg,
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u16 mask, u16 val)
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{
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struct net_device *dev = priv->ndev;
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int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val);
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if (unlikely(ret))
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netif_err(priv, drv, dev, "%s: error %d updating reg %02x=%04x~%04x\n",
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__func__, ret, reg, val, mask);
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}
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static u16 encx24j600_read_phy(struct encx24j600_priv *priv, u8 reg)
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{
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struct net_device *dev = priv->ndev;
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unsigned int val = 0;
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int ret = regmap_read(priv->ctx.phymap, reg, &val);
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if (unlikely(ret))
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netif_err(priv, drv, dev, "%s: error %d reading %02x\n",
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__func__, ret, reg);
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return val;
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}
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static void encx24j600_write_phy(struct encx24j600_priv *priv, u8 reg, u16 val)
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{
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struct net_device *dev = priv->ndev;
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int ret = regmap_write(priv->ctx.phymap, reg, val);
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if (unlikely(ret))
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netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
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__func__, ret, reg, val);
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}
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static void encx24j600_clr_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
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{
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encx24j600_update_reg(priv, reg, mask, 0);
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}
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static void encx24j600_set_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
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{
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encx24j600_update_reg(priv, reg, mask, mask);
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}
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static void encx24j600_cmd(struct encx24j600_priv *priv, u8 cmd)
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{
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struct net_device *dev = priv->ndev;
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int ret = regmap_write(priv->ctx.regmap, cmd, 0);
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if (unlikely(ret))
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netif_err(priv, drv, dev, "%s: error %d with cmd %02x\n",
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__func__, ret, cmd);
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}
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static int encx24j600_raw_read(struct encx24j600_priv *priv, u8 reg, u8 *data,
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size_t count)
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{
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int ret;
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mutex_lock(&priv->ctx.mutex);
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ret = regmap_encx24j600_spi_read(&priv->ctx, reg, data, count);
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mutex_unlock(&priv->ctx.mutex);
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return ret;
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}
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static int encx24j600_raw_write(struct encx24j600_priv *priv, u8 reg,
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const u8 *data, size_t count)
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{
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int ret;
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mutex_lock(&priv->ctx.mutex);
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ret = regmap_encx24j600_spi_write(&priv->ctx, reg, data, count);
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mutex_unlock(&priv->ctx.mutex);
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return ret;
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}
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static void encx24j600_update_phcon1(struct encx24j600_priv *priv)
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{
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u16 phcon1 = encx24j600_read_phy(priv, PHCON1);
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if (priv->autoneg == AUTONEG_ENABLE) {
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phcon1 |= ANEN | RENEG;
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} else {
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phcon1 &= ~ANEN;
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if (priv->speed == SPEED_100)
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phcon1 |= SPD100;
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else
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phcon1 &= ~SPD100;
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if (priv->full_duplex)
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phcon1 |= PFULDPX;
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else
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phcon1 &= ~PFULDPX;
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}
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encx24j600_write_phy(priv, PHCON1, phcon1);
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}
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/* Waits for autonegotiation to complete. */
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static int encx24j600_wait_for_autoneg(struct encx24j600_priv *priv)
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{
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struct net_device *dev = priv->ndev;
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unsigned long timeout = jiffies + msecs_to_jiffies(2000);
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u16 phstat1;
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u16 estat;
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phstat1 = encx24j600_read_phy(priv, PHSTAT1);
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while ((phstat1 & ANDONE) == 0) {
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if (time_after(jiffies, timeout)) {
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u16 phstat3;
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netif_notice(priv, drv, dev, "timeout waiting for autoneg done\n");
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priv->autoneg = AUTONEG_DISABLE;
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phstat3 = encx24j600_read_phy(priv, PHSTAT3);
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priv->speed = (phstat3 & PHY3SPD100)
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? SPEED_100 : SPEED_10;
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priv->full_duplex = (phstat3 & PHY3DPX) ? 1 : 0;
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encx24j600_update_phcon1(priv);
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netif_notice(priv, drv, dev, "Using parallel detection: %s/%s",
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priv->speed == SPEED_100 ? "100" : "10",
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priv->full_duplex ? "Full" : "Half");
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return -ETIMEDOUT;
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}
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cpu_relax();
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phstat1 = encx24j600_read_phy(priv, PHSTAT1);
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}
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estat = encx24j600_read_reg(priv, ESTAT);
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if (estat & PHYDPX) {
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encx24j600_set_bits(priv, MACON2, FULDPX);
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encx24j600_write_reg(priv, MABBIPG, 0x15);
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} else {
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encx24j600_clr_bits(priv, MACON2, FULDPX);
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encx24j600_write_reg(priv, MABBIPG, 0x12);
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/* Max retransmittions attempt */
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encx24j600_write_reg(priv, MACLCON, 0x370f);
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}
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return 0;
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}
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/* Access the PHY to determine link status */
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static void encx24j600_check_link_status(struct encx24j600_priv *priv)
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{
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struct net_device *dev = priv->ndev;
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u16 estat;
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estat = encx24j600_read_reg(priv, ESTAT);
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if (estat & PHYLNK) {
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if (priv->autoneg == AUTONEG_ENABLE)
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encx24j600_wait_for_autoneg(priv);
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netif_carrier_on(dev);
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netif_info(priv, ifup, dev, "link up\n");
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} else {
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netif_info(priv, ifdown, dev, "link down\n");
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/* Re-enable autoneg since we won't know what we might be
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* connected to when the link is brought back up again.
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*/
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priv->autoneg = AUTONEG_ENABLE;
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priv->full_duplex = true;
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priv->speed = SPEED_100;
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netif_carrier_off(dev);
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}
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}
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static void encx24j600_int_link_handler(struct encx24j600_priv *priv)
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{
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struct net_device *dev = priv->ndev;
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netif_dbg(priv, intr, dev, "%s", __func__);
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encx24j600_check_link_status(priv);
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encx24j600_clr_bits(priv, EIR, LINKIF);
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}
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static void encx24j600_tx_complete(struct encx24j600_priv *priv, bool err)
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{
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struct net_device *dev = priv->ndev;
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if (!priv->tx_skb) {
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BUG();
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return;
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}
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mutex_lock(&priv->lock);
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if (err)
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dev->stats.tx_errors++;
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else
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dev->stats.tx_packets++;
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dev->stats.tx_bytes += priv->tx_skb->len;
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encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
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netif_dbg(priv, tx_done, dev, "TX Done%s\n", err ? ": Err" : "");
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dev_kfree_skb(priv->tx_skb);
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priv->tx_skb = NULL;
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netif_wake_queue(dev);
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mutex_unlock(&priv->lock);
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}
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static int encx24j600_receive_packet(struct encx24j600_priv *priv,
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struct rsv *rsv)
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{
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struct net_device *dev = priv->ndev;
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struct sk_buff *skb = netdev_alloc_skb(dev, rsv->len + NET_IP_ALIGN);
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if (!skb) {
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pr_err_ratelimited("RX: OOM: packet dropped\n");
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dev->stats.rx_dropped++;
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return -ENOMEM;
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}
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skb_reserve(skb, NET_IP_ALIGN);
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encx24j600_raw_read(priv, RRXDATA, skb_put(skb, rsv->len), rsv->len);
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if (netif_msg_pktdata(priv))
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dump_packet("RX", skb->len, skb->data);
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skb->dev = dev;
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skb->protocol = eth_type_trans(skb, dev);
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skb->ip_summed = CHECKSUM_COMPLETE;
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/* Maintain stats */
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dev->stats.rx_packets++;
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dev->stats.rx_bytes += rsv->len;
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netif_rx(skb);
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return 0;
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}
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static void encx24j600_rx_packets(struct encx24j600_priv *priv, u8 packet_count)
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{
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struct net_device *dev = priv->ndev;
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while (packet_count--) {
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struct rsv rsv;
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u16 newrxtail;
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encx24j600_write_reg(priv, ERXRDPT, priv->next_packet);
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encx24j600_raw_read(priv, RRXDATA, (u8 *)&rsv, sizeof(rsv));
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if (netif_msg_rx_status(priv))
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encx24j600_dump_rsv(priv, __func__, &rsv);
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if (!RSV_GETBIT(rsv.rxstat, RSV_RXOK) ||
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(rsv.len > MAX_FRAMELEN)) {
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netif_err(priv, rx_err, dev, "RX Error %04x\n",
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rsv.rxstat);
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dev->stats.rx_errors++;
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if (RSV_GETBIT(rsv.rxstat, RSV_CRCERROR))
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dev->stats.rx_crc_errors++;
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if (RSV_GETBIT(rsv.rxstat, RSV_LENCHECKERR))
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dev->stats.rx_frame_errors++;
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if (rsv.len > MAX_FRAMELEN)
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dev->stats.rx_over_errors++;
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} else {
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encx24j600_receive_packet(priv, &rsv);
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}
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priv->next_packet = rsv.next_packet;
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newrxtail = priv->next_packet - 2;
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if (newrxtail == ENC_RX_BUF_START)
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newrxtail = SRAM_SIZE - 2;
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encx24j600_cmd(priv, SETPKTDEC);
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encx24j600_write_reg(priv, ERXTAIL, newrxtail);
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}
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}
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static irqreturn_t encx24j600_isr(int irq, void *dev_id)
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{
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struct encx24j600_priv *priv = dev_id;
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struct net_device *dev = priv->ndev;
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int eir;
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/* Clear interrupts */
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encx24j600_cmd(priv, CLREIE);
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eir = encx24j600_read_reg(priv, EIR);
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if (eir & LINKIF)
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encx24j600_int_link_handler(priv);
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if (eir & TXIF)
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encx24j600_tx_complete(priv, false);
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if (eir & TXABTIF)
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encx24j600_tx_complete(priv, true);
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if (eir & RXABTIF) {
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if (eir & PCFULIF) {
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/* Packet counter is full */
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netif_err(priv, rx_err, dev, "Packet counter full\n");
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}
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dev->stats.rx_dropped++;
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encx24j600_clr_bits(priv, EIR, RXABTIF);
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}
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if (eir & PKTIF) {
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u8 packet_count;
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mutex_lock(&priv->lock);
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packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
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while (packet_count) {
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encx24j600_rx_packets(priv, packet_count);
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packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
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}
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mutex_unlock(&priv->lock);
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}
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/* Enable interrupts */
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encx24j600_cmd(priv, SETEIE);
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return IRQ_HANDLED;
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}
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static int encx24j600_soft_reset(struct encx24j600_priv *priv)
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{
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int ret = 0;
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int timeout;
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u16 eudast;
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/* Write and verify a test value to EUDAST */
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regcache_cache_bypass(priv->ctx.regmap, true);
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timeout = 10;
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do {
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encx24j600_write_reg(priv, EUDAST, EUDAST_TEST_VAL);
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eudast = encx24j600_read_reg(priv, EUDAST);
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usleep_range(25, 100);
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} while ((eudast != EUDAST_TEST_VAL) && --timeout);
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regcache_cache_bypass(priv->ctx.regmap, false);
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if (timeout == 0) {
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ret = -ETIMEDOUT;
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goto err_out;
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}
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/* Wait for CLKRDY to become set */
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timeout = 10;
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while (!(encx24j600_read_reg(priv, ESTAT) & CLKRDY) && --timeout)
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usleep_range(25, 100);
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if (timeout == 0) {
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ret = -ETIMEDOUT;
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goto err_out;
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}
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|
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/* Issue a System Reset command */
|
|
encx24j600_cmd(priv, SETETHRST);
|
|
usleep_range(25, 100);
|
|
|
|
/* Confirm that EUDAST has 0000h after system reset */
|
|
if (encx24j600_read_reg(priv, EUDAST) != 0) {
|
|
ret = -EINVAL;
|
|
goto err_out;
|
|
}
|
|
|
|
/* Wait for PHY register and status bits to become available */
|
|
usleep_range(256, 1000);
|
|
|
|
err_out:
|
|
return ret;
|
|
}
|
|
|
|
static int encx24j600_hw_reset(struct encx24j600_priv *priv)
|
|
{
|
|
int ret;
|
|
|
|
mutex_lock(&priv->lock);
|
|
ret = encx24j600_soft_reset(priv);
|
|
mutex_unlock(&priv->lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void encx24j600_reset_hw_tx(struct encx24j600_priv *priv)
|
|
{
|
|
encx24j600_set_bits(priv, ECON2, TXRST);
|
|
encx24j600_clr_bits(priv, ECON2, TXRST);
|
|
}
|
|
|
|
static void encx24j600_hw_init_tx(struct encx24j600_priv *priv)
|
|
{
|
|
/* Reset TX */
|
|
encx24j600_reset_hw_tx(priv);
|
|
|
|
/* Clear the TXIF flag if were previously set */
|
|
encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
|
|
|
|
/* Write the Tx Buffer pointer */
|
|
encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
|
|
}
|
|
|
|
static void encx24j600_hw_init_rx(struct encx24j600_priv *priv)
|
|
{
|
|
encx24j600_cmd(priv, DISABLERX);
|
|
|
|
/* Set up RX packet start address in the SRAM */
|
|
encx24j600_write_reg(priv, ERXST, ENC_RX_BUF_START);
|
|
|
|
/* Preload the RX Data pointer to the beginning of the RX area */
|
|
encx24j600_write_reg(priv, ERXRDPT, ENC_RX_BUF_START);
|
|
|
|
priv->next_packet = ENC_RX_BUF_START;
|
|
|
|
/* Set up RX end address in the SRAM */
|
|
encx24j600_write_reg(priv, ERXTAIL, ENC_SRAM_SIZE - 2);
|
|
|
|
/* Reset the user data pointers */
|
|
encx24j600_write_reg(priv, EUDAST, ENC_SRAM_SIZE);
|
|
encx24j600_write_reg(priv, EUDAND, ENC_SRAM_SIZE + 1);
|
|
|
|
/* Set Max Frame length */
|
|
encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
|
|
}
|
|
|
|
static void encx24j600_dump_config(struct encx24j600_priv *priv,
|
|
const char *msg)
|
|
{
|
|
pr_info(DRV_NAME ": %s\n", msg);
|
|
|
|
/* CHIP configuration */
|
|
pr_info(DRV_NAME " ECON1: %04X\n", encx24j600_read_reg(priv, ECON1));
|
|
pr_info(DRV_NAME " ECON2: %04X\n", encx24j600_read_reg(priv, ECON2));
|
|
pr_info(DRV_NAME " ERXFCON: %04X\n", encx24j600_read_reg(priv,
|
|
ERXFCON));
|
|
pr_info(DRV_NAME " ESTAT: %04X\n", encx24j600_read_reg(priv, ESTAT));
|
|
pr_info(DRV_NAME " EIR: %04X\n", encx24j600_read_reg(priv, EIR));
|
|
pr_info(DRV_NAME " EIDLED: %04X\n", encx24j600_read_reg(priv, EIDLED));
|
|
|
|
/* MAC layer configuration */
|
|
pr_info(DRV_NAME " MACON1: %04X\n", encx24j600_read_reg(priv, MACON1));
|
|
pr_info(DRV_NAME " MACON2: %04X\n", encx24j600_read_reg(priv, MACON2));
|
|
pr_info(DRV_NAME " MAIPG: %04X\n", encx24j600_read_reg(priv, MAIPG));
|
|
pr_info(DRV_NAME " MACLCON: %04X\n", encx24j600_read_reg(priv,
|
|
MACLCON));
|
|
pr_info(DRV_NAME " MABBIPG: %04X\n", encx24j600_read_reg(priv,
|
|
MABBIPG));
|
|
|
|
/* PHY configuation */
|
|
pr_info(DRV_NAME " PHCON1: %04X\n", encx24j600_read_phy(priv, PHCON1));
|
|
pr_info(DRV_NAME " PHCON2: %04X\n", encx24j600_read_phy(priv, PHCON2));
|
|
pr_info(DRV_NAME " PHANA: %04X\n", encx24j600_read_phy(priv, PHANA));
|
|
pr_info(DRV_NAME " PHANLPA: %04X\n", encx24j600_read_phy(priv,
|
|
PHANLPA));
|
|
pr_info(DRV_NAME " PHANE: %04X\n", encx24j600_read_phy(priv, PHANE));
|
|
pr_info(DRV_NAME " PHSTAT1: %04X\n", encx24j600_read_phy(priv,
|
|
PHSTAT1));
|
|
pr_info(DRV_NAME " PHSTAT2: %04X\n", encx24j600_read_phy(priv,
|
|
PHSTAT2));
|
|
pr_info(DRV_NAME " PHSTAT3: %04X\n", encx24j600_read_phy(priv,
|
|
PHSTAT3));
|
|
}
|
|
|
|
static void encx24j600_set_rxfilter_mode(struct encx24j600_priv *priv)
|
|
{
|
|
switch (priv->rxfilter) {
|
|
case RXFILTER_PROMISC:
|
|
encx24j600_set_bits(priv, MACON1, PASSALL);
|
|
encx24j600_write_reg(priv, ERXFCON, UCEN | MCEN | NOTMEEN);
|
|
break;
|
|
case RXFILTER_MULTI:
|
|
encx24j600_clr_bits(priv, MACON1, PASSALL);
|
|
encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN | MCEN);
|
|
break;
|
|
case RXFILTER_NORMAL:
|
|
default:
|
|
encx24j600_clr_bits(priv, MACON1, PASSALL);
|
|
encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void encx24j600_hw_init(struct encx24j600_priv *priv)
|
|
{
|
|
u16 macon2;
|
|
|
|
priv->hw_enabled = false;
|
|
|
|
/* PHY Leds: link status,
|
|
* LEDA: Link State + collision events
|
|
* LEDB: Link State + transmit/receive events
|
|
*/
|
|
encx24j600_update_reg(priv, EIDLED, 0xff00, 0xcb00);
|
|
|
|
/* Loopback disabled */
|
|
encx24j600_write_reg(priv, MACON1, 0x9);
|
|
|
|
/* interpacket gap value */
|
|
encx24j600_write_reg(priv, MAIPG, 0x0c12);
|
|
|
|
/* Write the auto negotiation pattern */
|
|
encx24j600_write_phy(priv, PHANA, PHANA_DEFAULT);
|
|
|
|
encx24j600_update_phcon1(priv);
|
|
encx24j600_check_link_status(priv);
|
|
|
|
macon2 = MACON2_RSV1 | TXCRCEN | PADCFG0 | PADCFG2 | MACON2_DEFER;
|
|
if ((priv->autoneg == AUTONEG_DISABLE) && priv->full_duplex)
|
|
macon2 |= FULDPX;
|
|
|
|
encx24j600_set_bits(priv, MACON2, macon2);
|
|
|
|
priv->rxfilter = RXFILTER_NORMAL;
|
|
encx24j600_set_rxfilter_mode(priv);
|
|
|
|
/* Program the Maximum frame length */
|
|
encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
|
|
|
|
/* Init Tx pointers */
|
|
encx24j600_hw_init_tx(priv);
|
|
|
|
/* Init Rx pointers */
|
|
encx24j600_hw_init_rx(priv);
|
|
|
|
if (netif_msg_hw(priv))
|
|
encx24j600_dump_config(priv, "Hw is initialized");
|
|
}
|
|
|
|
static void encx24j600_hw_enable(struct encx24j600_priv *priv)
|
|
{
|
|
/* Clear the interrupt flags in case was set */
|
|
encx24j600_clr_bits(priv, EIR, (PCFULIF | RXABTIF | TXABTIF | TXIF |
|
|
PKTIF | LINKIF));
|
|
|
|
/* Enable the interrupts */
|
|
encx24j600_write_reg(priv, EIE, (PCFULIE | RXABTIE | TXABTIE | TXIE |
|
|
PKTIE | LINKIE | INTIE));
|
|
|
|
/* Enable RX */
|
|
encx24j600_cmd(priv, ENABLERX);
|
|
|
|
priv->hw_enabled = true;
|
|
}
|
|
|
|
static void encx24j600_hw_disable(struct encx24j600_priv *priv)
|
|
{
|
|
/* Disable all interrupts */
|
|
encx24j600_write_reg(priv, EIE, 0);
|
|
|
|
/* Disable RX */
|
|
encx24j600_cmd(priv, DISABLERX);
|
|
|
|
priv->hw_enabled = false;
|
|
}
|
|
|
|
static int encx24j600_setlink(struct net_device *dev, u8 autoneg, u16 speed,
|
|
u8 duplex)
|
|
{
|
|
struct encx24j600_priv *priv = netdev_priv(dev);
|
|
int ret = 0;
|
|
|
|
if (!priv->hw_enabled) {
|
|
/* link is in low power mode now; duplex setting
|
|
* will take effect on next encx24j600_hw_init()
|
|
*/
|
|
if (speed == SPEED_10 || speed == SPEED_100) {
|
|
priv->autoneg = (autoneg == AUTONEG_ENABLE);
|
|
priv->full_duplex = (duplex == DUPLEX_FULL);
|
|
priv->speed = (speed == SPEED_100);
|
|
} else {
|
|
netif_warn(priv, link, dev, "unsupported link speed setting\n");
|
|
/*speeds other than SPEED_10 and SPEED_100 */
|
|
/*are not supported by chip */
|
|
ret = -EOPNOTSUPP;
|
|
}
|
|
} else {
|
|
netif_warn(priv, link, dev, "Warning: hw must be disabled to set link mode\n");
|
|
ret = -EBUSY;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void encx24j600_hw_get_macaddr(struct encx24j600_priv *priv,
|
|
unsigned char *ethaddr)
|
|
{
|
|
unsigned short val;
|
|
|
|
val = encx24j600_read_reg(priv, MAADR1);
|
|
|
|
ethaddr[0] = val & 0x00ff;
|
|
ethaddr[1] = (val & 0xff00) >> 8;
|
|
|
|
val = encx24j600_read_reg(priv, MAADR2);
|
|
|
|
ethaddr[2] = val & 0x00ffU;
|
|
ethaddr[3] = (val & 0xff00U) >> 8;
|
|
|
|
val = encx24j600_read_reg(priv, MAADR3);
|
|
|
|
ethaddr[4] = val & 0x00ffU;
|
|
ethaddr[5] = (val & 0xff00U) >> 8;
|
|
}
|
|
|
|
/* Program the hardware MAC address from dev->dev_addr.*/
|
|
static int encx24j600_set_hw_macaddr(struct net_device *dev)
|
|
{
|
|
struct encx24j600_priv *priv = netdev_priv(dev);
|
|
|
|
if (priv->hw_enabled) {
|
|
netif_info(priv, drv, dev, "Hardware must be disabled to set Mac address\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
mutex_lock(&priv->lock);
|
|
|
|
netif_info(priv, drv, dev, "%s: Setting MAC address to %pM\n",
|
|
dev->name, dev->dev_addr);
|
|
|
|
encx24j600_write_reg(priv, MAADR3, (dev->dev_addr[4] |
|
|
dev->dev_addr[5] << 8));
|
|
encx24j600_write_reg(priv, MAADR2, (dev->dev_addr[2] |
|
|
dev->dev_addr[3] << 8));
|
|
encx24j600_write_reg(priv, MAADR1, (dev->dev_addr[0] |
|
|
dev->dev_addr[1] << 8));
|
|
|
|
mutex_unlock(&priv->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Store the new hardware address in dev->dev_addr, and update the MAC.*/
|
|
static int encx24j600_set_mac_address(struct net_device *dev, void *addr)
|
|
{
|
|
struct sockaddr *address = addr;
|
|
|
|
if (netif_running(dev))
|
|
return -EBUSY;
|
|
if (!is_valid_ether_addr(address->sa_data))
|
|
return -EADDRNOTAVAIL;
|
|
|
|
eth_hw_addr_set(dev, address->sa_data);
|
|
return encx24j600_set_hw_macaddr(dev);
|
|
}
|
|
|
|
static int encx24j600_open(struct net_device *dev)
|
|
{
|
|
struct encx24j600_priv *priv = netdev_priv(dev);
|
|
|
|
int ret = request_threaded_irq(priv->ctx.spi->irq, NULL, encx24j600_isr,
|
|
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
|
|
DRV_NAME, priv);
|
|
if (unlikely(ret < 0)) {
|
|
netdev_err(dev, "request irq %d failed (ret = %d)\n",
|
|
priv->ctx.spi->irq, ret);
|
|
return ret;
|
|
}
|
|
|
|
encx24j600_hw_disable(priv);
|
|
encx24j600_hw_init(priv);
|
|
encx24j600_hw_enable(priv);
|
|
netif_start_queue(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int encx24j600_stop(struct net_device *dev)
|
|
{
|
|
struct encx24j600_priv *priv = netdev_priv(dev);
|
|
|
|
netif_stop_queue(dev);
|
|
free_irq(priv->ctx.spi->irq, priv);
|
|
return 0;
|
|
}
|
|
|
|
static void encx24j600_setrx_proc(struct kthread_work *ws)
|
|
{
|
|
struct encx24j600_priv *priv =
|
|
container_of(ws, struct encx24j600_priv, setrx_work);
|
|
|
|
mutex_lock(&priv->lock);
|
|
encx24j600_set_rxfilter_mode(priv);
|
|
mutex_unlock(&priv->lock);
|
|
}
|
|
|
|
static void encx24j600_set_multicast_list(struct net_device *dev)
|
|
{
|
|
struct encx24j600_priv *priv = netdev_priv(dev);
|
|
int oldfilter = priv->rxfilter;
|
|
|
|
if (dev->flags & IFF_PROMISC) {
|
|
netif_dbg(priv, link, dev, "promiscuous mode\n");
|
|
priv->rxfilter = RXFILTER_PROMISC;
|
|
} else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
|
|
netif_dbg(priv, link, dev, "%smulticast mode\n",
|
|
(dev->flags & IFF_ALLMULTI) ? "all-" : "");
|
|
priv->rxfilter = RXFILTER_MULTI;
|
|
} else {
|
|
netif_dbg(priv, link, dev, "normal mode\n");
|
|
priv->rxfilter = RXFILTER_NORMAL;
|
|
}
|
|
|
|
if (oldfilter != priv->rxfilter)
|
|
kthread_queue_work(&priv->kworker, &priv->setrx_work);
|
|
}
|
|
|
|
static void encx24j600_hw_tx(struct encx24j600_priv *priv)
|
|
{
|
|
struct net_device *dev = priv->ndev;
|
|
|
|
netif_info(priv, tx_queued, dev, "TX Packet Len:%d\n",
|
|
priv->tx_skb->len);
|
|
|
|
if (netif_msg_pktdata(priv))
|
|
dump_packet("TX", priv->tx_skb->len, priv->tx_skb->data);
|
|
|
|
if (encx24j600_read_reg(priv, EIR) & TXABTIF)
|
|
/* Last transmition aborted due to error. Reset TX interface */
|
|
encx24j600_reset_hw_tx(priv);
|
|
|
|
/* Clear the TXIF flag if were previously set */
|
|
encx24j600_clr_bits(priv, EIR, TXIF);
|
|
|
|
/* Set the data pointer to the TX buffer address in the SRAM */
|
|
encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
|
|
|
|
/* Copy the packet into the SRAM */
|
|
encx24j600_raw_write(priv, WGPDATA, (u8 *)priv->tx_skb->data,
|
|
priv->tx_skb->len);
|
|
|
|
/* Program the Tx buffer start pointer */
|
|
encx24j600_write_reg(priv, ETXST, ENC_TX_BUF_START);
|
|
|
|
/* Program the packet length */
|
|
encx24j600_write_reg(priv, ETXLEN, priv->tx_skb->len);
|
|
|
|
/* Start the transmission */
|
|
encx24j600_cmd(priv, SETTXRTS);
|
|
}
|
|
|
|
static void encx24j600_tx_proc(struct kthread_work *ws)
|
|
{
|
|
struct encx24j600_priv *priv =
|
|
container_of(ws, struct encx24j600_priv, tx_work);
|
|
|
|
mutex_lock(&priv->lock);
|
|
encx24j600_hw_tx(priv);
|
|
mutex_unlock(&priv->lock);
|
|
}
|
|
|
|
static netdev_tx_t encx24j600_tx(struct sk_buff *skb, struct net_device *dev)
|
|
{
|
|
struct encx24j600_priv *priv = netdev_priv(dev);
|
|
|
|
netif_stop_queue(dev);
|
|
|
|
/* save the timestamp */
|
|
netif_trans_update(dev);
|
|
|
|
/* Remember the skb for deferred processing */
|
|
priv->tx_skb = skb;
|
|
|
|
kthread_queue_work(&priv->kworker, &priv->tx_work);
|
|
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
/* Deal with a transmit timeout */
|
|
static void encx24j600_tx_timeout(struct net_device *dev, unsigned int txqueue)
|
|
{
|
|
struct encx24j600_priv *priv = netdev_priv(dev);
|
|
|
|
netif_err(priv, tx_err, dev, "TX timeout at %ld, latency %ld\n",
|
|
jiffies, jiffies - dev_trans_start(dev));
|
|
|
|
dev->stats.tx_errors++;
|
|
netif_wake_queue(dev);
|
|
}
|
|
|
|
static int encx24j600_get_regs_len(struct net_device *dev)
|
|
{
|
|
return SFR_REG_COUNT;
|
|
}
|
|
|
|
static void encx24j600_get_regs(struct net_device *dev,
|
|
struct ethtool_regs *regs, void *p)
|
|
{
|
|
struct encx24j600_priv *priv = netdev_priv(dev);
|
|
u16 *buff = p;
|
|
u8 reg;
|
|
|
|
regs->version = 1;
|
|
mutex_lock(&priv->lock);
|
|
for (reg = 0; reg < SFR_REG_COUNT; reg += 2) {
|
|
unsigned int val = 0;
|
|
/* ignore errors for unreadable registers */
|
|
regmap_read(priv->ctx.regmap, reg, &val);
|
|
buff[reg] = val & 0xffff;
|
|
}
|
|
mutex_unlock(&priv->lock);
|
|
}
|
|
|
|
static void encx24j600_get_drvinfo(struct net_device *dev,
|
|
struct ethtool_drvinfo *info)
|
|
{
|
|
strscpy(info->driver, DRV_NAME, sizeof(info->driver));
|
|
strscpy(info->version, DRV_VERSION, sizeof(info->version));
|
|
strscpy(info->bus_info, dev_name(dev->dev.parent),
|
|
sizeof(info->bus_info));
|
|
}
|
|
|
|
static int encx24j600_get_link_ksettings(struct net_device *dev,
|
|
struct ethtool_link_ksettings *cmd)
|
|
{
|
|
struct encx24j600_priv *priv = netdev_priv(dev);
|
|
u32 supported;
|
|
|
|
supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
|
|
SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
|
|
SUPPORTED_Autoneg | SUPPORTED_TP;
|
|
|
|
ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
|
|
supported);
|
|
|
|
cmd->base.speed = priv->speed;
|
|
cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
|
|
cmd->base.port = PORT_TP;
|
|
cmd->base.autoneg = priv->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
encx24j600_set_link_ksettings(struct net_device *dev,
|
|
const struct ethtool_link_ksettings *cmd)
|
|
{
|
|
return encx24j600_setlink(dev, cmd->base.autoneg,
|
|
cmd->base.speed, cmd->base.duplex);
|
|
}
|
|
|
|
static u32 encx24j600_get_msglevel(struct net_device *dev)
|
|
{
|
|
struct encx24j600_priv *priv = netdev_priv(dev);
|
|
|
|
return priv->msg_enable;
|
|
}
|
|
|
|
static void encx24j600_set_msglevel(struct net_device *dev, u32 val)
|
|
{
|
|
struct encx24j600_priv *priv = netdev_priv(dev);
|
|
|
|
priv->msg_enable = val;
|
|
}
|
|
|
|
static const struct ethtool_ops encx24j600_ethtool_ops = {
|
|
.get_drvinfo = encx24j600_get_drvinfo,
|
|
.get_msglevel = encx24j600_get_msglevel,
|
|
.set_msglevel = encx24j600_set_msglevel,
|
|
.get_regs_len = encx24j600_get_regs_len,
|
|
.get_regs = encx24j600_get_regs,
|
|
.get_link_ksettings = encx24j600_get_link_ksettings,
|
|
.set_link_ksettings = encx24j600_set_link_ksettings,
|
|
};
|
|
|
|
static const struct net_device_ops encx24j600_netdev_ops = {
|
|
.ndo_open = encx24j600_open,
|
|
.ndo_stop = encx24j600_stop,
|
|
.ndo_start_xmit = encx24j600_tx,
|
|
.ndo_set_rx_mode = encx24j600_set_multicast_list,
|
|
.ndo_set_mac_address = encx24j600_set_mac_address,
|
|
.ndo_tx_timeout = encx24j600_tx_timeout,
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
};
|
|
|
|
static int encx24j600_spi_probe(struct spi_device *spi)
|
|
{
|
|
int ret;
|
|
|
|
struct net_device *ndev;
|
|
struct encx24j600_priv *priv;
|
|
u16 eidled;
|
|
u8 addr[ETH_ALEN];
|
|
|
|
ndev = alloc_etherdev(sizeof(struct encx24j600_priv));
|
|
|
|
if (!ndev) {
|
|
ret = -ENOMEM;
|
|
goto error_out;
|
|
}
|
|
|
|
priv = netdev_priv(ndev);
|
|
spi_set_drvdata(spi, priv);
|
|
dev_set_drvdata(&spi->dev, priv);
|
|
SET_NETDEV_DEV(ndev, &spi->dev);
|
|
|
|
priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
|
|
priv->ndev = ndev;
|
|
|
|
/* Default configuration PHY configuration */
|
|
priv->full_duplex = true;
|
|
priv->autoneg = AUTONEG_ENABLE;
|
|
priv->speed = SPEED_100;
|
|
|
|
priv->ctx.spi = spi;
|
|
ndev->irq = spi->irq;
|
|
ndev->netdev_ops = &encx24j600_netdev_ops;
|
|
|
|
ret = devm_regmap_init_encx24j600(&spi->dev, &priv->ctx);
|
|
if (ret)
|
|
goto out_free;
|
|
|
|
mutex_init(&priv->lock);
|
|
|
|
/* Reset device and check if it is connected */
|
|
if (encx24j600_hw_reset(priv)) {
|
|
netif_err(priv, probe, ndev,
|
|
DRV_NAME ": Chip is not detected\n");
|
|
ret = -EIO;
|
|
goto out_free;
|
|
}
|
|
|
|
/* Initialize the device HW to the consistent state */
|
|
encx24j600_hw_init(priv);
|
|
|
|
kthread_init_worker(&priv->kworker);
|
|
kthread_init_work(&priv->tx_work, encx24j600_tx_proc);
|
|
kthread_init_work(&priv->setrx_work, encx24j600_setrx_proc);
|
|
|
|
priv->kworker_task = kthread_run(kthread_worker_fn, &priv->kworker,
|
|
"encx24j600");
|
|
|
|
if (IS_ERR(priv->kworker_task)) {
|
|
ret = PTR_ERR(priv->kworker_task);
|
|
goto out_free;
|
|
}
|
|
|
|
/* Get the MAC address from the chip */
|
|
encx24j600_hw_get_macaddr(priv, addr);
|
|
eth_hw_addr_set(ndev, addr);
|
|
|
|
ndev->ethtool_ops = &encx24j600_ethtool_ops;
|
|
|
|
ret = register_netdev(ndev);
|
|
if (unlikely(ret)) {
|
|
netif_err(priv, probe, ndev, "Error %d initializing card encx24j600 card\n",
|
|
ret);
|
|
goto out_stop;
|
|
}
|
|
|
|
eidled = encx24j600_read_reg(priv, EIDLED);
|
|
if (((eidled & DEVID_MASK) >> DEVID_SHIFT) != ENCX24J600_DEV_ID) {
|
|
ret = -EINVAL;
|
|
goto out_unregister;
|
|
}
|
|
|
|
netif_info(priv, probe, ndev, "Silicon rev ID: 0x%02x\n",
|
|
(eidled & REVID_MASK) >> REVID_SHIFT);
|
|
|
|
netif_info(priv, drv, priv->ndev, "MAC address %pM\n", ndev->dev_addr);
|
|
|
|
return ret;
|
|
|
|
out_unregister:
|
|
unregister_netdev(priv->ndev);
|
|
out_stop:
|
|
kthread_stop(priv->kworker_task);
|
|
out_free:
|
|
free_netdev(ndev);
|
|
|
|
error_out:
|
|
return ret;
|
|
}
|
|
|
|
static void encx24j600_spi_remove(struct spi_device *spi)
|
|
{
|
|
struct encx24j600_priv *priv = dev_get_drvdata(&spi->dev);
|
|
|
|
unregister_netdev(priv->ndev);
|
|
kthread_stop(priv->kworker_task);
|
|
|
|
free_netdev(priv->ndev);
|
|
}
|
|
|
|
static const struct spi_device_id encx24j600_spi_id_table[] = {
|
|
{ .name = "encx24j600" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(spi, encx24j600_spi_id_table);
|
|
|
|
static struct spi_driver encx24j600_spi_net_driver = {
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.bus = &spi_bus_type,
|
|
},
|
|
.probe = encx24j600_spi_probe,
|
|
.remove = encx24j600_spi_remove,
|
|
.id_table = encx24j600_spi_id_table,
|
|
};
|
|
|
|
module_spi_driver(encx24j600_spi_net_driver);
|
|
|
|
MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
|
|
MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
|
|
MODULE_LICENSE("GPL");
|