92 lines
3.7 KiB
C
92 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/******************************************************************************
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PTP Header file
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Copyright (C) 2013 Vayavya Labs Pvt Ltd
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Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
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******************************************************************************/
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#ifndef __STMMAC_PTP_H__
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#define __STMMAC_PTP_H__
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#define PTP_XGMAC_OFFSET 0xd00
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#define PTP_GMAC4_OFFSET 0xb00
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#define PTP_GMAC3_X_OFFSET 0x700
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/* IEEE 1588 PTP register offsets */
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#define PTP_TCR 0x00 /* Timestamp Control Reg */
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#define PTP_SSIR 0x04 /* Sub-Second Increment Reg */
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#define PTP_STSR 0x08 /* System Time – Seconds Regr */
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#define PTP_STNSR 0x0c /* System Time – Nanoseconds Reg */
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#define PTP_STSUR 0x10 /* System Time – Seconds Update Reg */
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#define PTP_STNSUR 0x14 /* System Time – Nanoseconds Update Reg */
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#define PTP_TAR 0x18 /* Timestamp Addend Reg */
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#define PTP_ACR 0x40 /* Auxiliary Control Reg */
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#define PTP_ATNR 0x48 /* Auxiliary Timestamp - Nanoseconds Reg */
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#define PTP_ATSR 0x4c /* Auxiliary Timestamp - Seconds Reg */
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#define PTP_STNSUR_ADDSUB_SHIFT 31
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#define PTP_DIGITAL_ROLLOVER_MODE 0x3B9ACA00 /* 10e9-1 ns */
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#define PTP_BINARY_ROLLOVER_MODE 0x80000000 /* ~0.466 ns */
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/* PTP Timestamp control register defines */
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#define PTP_TCR_TSENA BIT(0) /* Timestamp Enable */
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#define PTP_TCR_TSCFUPDT BIT(1) /* Timestamp Fine/Coarse Update */
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#define PTP_TCR_TSINIT BIT(2) /* Timestamp Initialize */
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#define PTP_TCR_TSUPDT BIT(3) /* Timestamp Update */
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#define PTP_TCR_TSTRIG BIT(4) /* Timestamp Interrupt Trigger Enable */
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#define PTP_TCR_TSADDREG BIT(5) /* Addend Reg Update */
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#define PTP_TCR_TSENALL BIT(8) /* Enable Timestamp for All Frames */
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#define PTP_TCR_TSCTRLSSR BIT(9) /* Digital or Binary Rollover Control */
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/* Enable PTP packet Processing for Version 2 Format */
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#define PTP_TCR_TSVER2ENA BIT(10)
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/* Enable Processing of PTP over Ethernet Frames */
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#define PTP_TCR_TSIPENA BIT(11)
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/* Enable Processing of PTP Frames Sent over IPv6-UDP */
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#define PTP_TCR_TSIPV6ENA BIT(12)
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/* Enable Processing of PTP Frames Sent over IPv4-UDP */
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#define PTP_TCR_TSIPV4ENA BIT(13)
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/* Enable Timestamp Snapshot for Event Messages */
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#define PTP_TCR_TSEVNTENA BIT(14)
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/* Enable Snapshot for Messages Relevant to Master */
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#define PTP_TCR_TSMSTRENA BIT(15)
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/* Select PTP packets for Taking Snapshots
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* On gmac4 specifically:
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* Enable SYNC, Pdelay_Req, Pdelay_Resp when TSEVNTENA is enabled.
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* or
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* Enable SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp,
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* Pdelay_Resp_Follow_Up if TSEVNTENA is disabled
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*/
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#define PTP_TCR_SNAPTYPSEL_1 BIT(16)
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/* Enable MAC address for PTP Frame Filtering */
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#define PTP_TCR_TSENMACADDR BIT(18)
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/* SSIR defines */
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#define PTP_SSIR_SSINC_MAX 0xff
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#define GMAC4_PTP_SSIR_SSINC_SHIFT 16
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/* Auxiliary Control defines */
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#define PTP_ACR_ATSFC BIT(0) /* Auxiliary Snapshot FIFO Clear */
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#define PTP_ACR_ATSEN0 BIT(4) /* Auxiliary Snapshot 0 Enable */
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#define PTP_ACR_ATSEN1 BIT(5) /* Auxiliary Snapshot 1 Enable */
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#define PTP_ACR_ATSEN2 BIT(6) /* Auxiliary Snapshot 2 Enable */
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#define PTP_ACR_ATSEN3 BIT(7) /* Auxiliary Snapshot 3 Enable */
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#define PTP_ACR_ATSEN_SHIFT 5 /* Auxiliary Snapshot shift */
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#define PTP_ACR_MASK GENMASK(7, 4) /* Aux Snapshot Mask */
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#define PMC_ART_VALUE0 0x01 /* PMC_ART[15:0] timer value */
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#define PMC_ART_VALUE1 0x02 /* PMC_ART[31:16] timer value */
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#define PMC_ART_VALUE2 0x03 /* PMC_ART[47:32] timer value */
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#define PMC_ART_VALUE3 0x04 /* PMC_ART[63:48] timer value */
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#define GMAC4_ART_TIME_SHIFT 16 /* ART TIME 16-bits shift */
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enum aux_snapshot {
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AUX_SNAPSHOT0 = 0x10,
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AUX_SNAPSHOT1 = 0x20,
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AUX_SNAPSHOT2 = 0x40,
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AUX_SNAPSHOT3 = 0x80,
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};
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#endif /* __STMMAC_PTP_H__ */
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