628 lines
18 KiB
C
628 lines
18 KiB
C
/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2017 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copy
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Intel PCIe GEN3 NTB Linux driver
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*
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*/
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/random.h>
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#include <linux/slab.h>
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#include <linux/ntb.h>
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#include "ntb_hw_intel.h"
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#include "ntb_hw_gen1.h"
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#include "ntb_hw_gen3.h"
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static int gen3_poll_link(struct intel_ntb_dev *ndev);
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static const struct intel_ntb_reg gen3_reg = {
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.poll_link = gen3_poll_link,
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.link_is_up = xeon_link_is_up,
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.db_ioread = gen3_db_ioread,
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.db_iowrite = gen3_db_iowrite,
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.db_size = sizeof(u32),
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.ntb_ctl = GEN3_NTBCNTL_OFFSET,
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.mw_bar = {2, 4},
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};
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static const struct intel_ntb_alt_reg gen3_pri_reg = {
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.db_bell = GEN3_EM_DOORBELL_OFFSET,
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.db_clear = GEN3_IM_INT_STATUS_OFFSET,
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.db_mask = GEN3_IM_INT_DISABLE_OFFSET,
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.spad = GEN3_IM_SPAD_OFFSET,
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};
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static const struct intel_ntb_alt_reg gen3_b2b_reg = {
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.db_bell = GEN3_IM_DOORBELL_OFFSET,
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.db_clear = GEN3_EM_INT_STATUS_OFFSET,
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.db_mask = GEN3_EM_INT_DISABLE_OFFSET,
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.spad = GEN3_B2B_SPAD_OFFSET,
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};
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static const struct intel_ntb_xlat_reg gen3_sec_xlat = {
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/* .bar0_base = GEN3_EMBAR0_OFFSET, */
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.bar2_limit = GEN3_IMBAR1XLMT_OFFSET,
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.bar2_xlat = GEN3_IMBAR1XBASE_OFFSET,
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};
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static int gen3_poll_link(struct intel_ntb_dev *ndev)
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{
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u16 reg_val;
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int rc;
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ndev->reg->db_iowrite(ndev->db_link_mask,
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ndev->self_mmio +
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ndev->self_reg->db_clear);
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rc = pci_read_config_word(ndev->ntb.pdev,
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GEN3_LINK_STATUS_OFFSET, ®_val);
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if (rc)
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return 0;
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if (reg_val == ndev->lnk_sta)
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return 0;
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ndev->lnk_sta = reg_val;
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return 1;
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}
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static int gen3_init_isr(struct intel_ntb_dev *ndev)
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{
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int i;
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/*
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* The MSIX vectors and the interrupt status bits are not lined up
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* on Skylake. By default the link status bit is bit 32, however it
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* is by default MSIX vector0. We need to fixup to line them up.
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* The vectors at reset is 1-32,0. We need to reprogram to 0-32.
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*/
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for (i = 0; i < GEN3_DB_MSIX_VECTOR_COUNT; i++)
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iowrite8(i, ndev->self_mmio + GEN3_INTVEC_OFFSET + i);
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/* move link status down one as workaround */
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if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) {
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iowrite8(GEN3_DB_MSIX_VECTOR_COUNT - 2,
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ndev->self_mmio + GEN3_INTVEC_OFFSET +
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(GEN3_DB_MSIX_VECTOR_COUNT - 1));
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}
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return ndev_init_isr(ndev, GEN3_DB_MSIX_VECTOR_COUNT,
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GEN3_DB_MSIX_VECTOR_COUNT,
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GEN3_DB_MSIX_VECTOR_SHIFT,
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GEN3_DB_TOTAL_SHIFT);
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}
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static int gen3_setup_b2b_mw(struct intel_ntb_dev *ndev,
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const struct intel_b2b_addr *addr,
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const struct intel_b2b_addr *peer_addr)
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{
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struct pci_dev *pdev;
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void __iomem *mmio;
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phys_addr_t bar_addr;
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pdev = ndev->ntb.pdev;
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mmio = ndev->self_mmio;
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/* setup incoming bar limits == base addrs (zero length windows) */
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bar_addr = addr->bar2_addr64;
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iowrite64(bar_addr, mmio + GEN3_IMBAR1XLMT_OFFSET);
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bar_addr = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);
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dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr);
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bar_addr = addr->bar4_addr64;
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iowrite64(bar_addr, mmio + GEN3_IMBAR2XLMT_OFFSET);
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bar_addr = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);
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dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr);
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/* zero incoming translation addrs */
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iowrite64(0, mmio + GEN3_IMBAR1XBASE_OFFSET);
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iowrite64(0, mmio + GEN3_IMBAR2XBASE_OFFSET);
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ndev->peer_mmio = ndev->self_mmio;
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return 0;
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}
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static int gen3_init_ntb(struct intel_ntb_dev *ndev)
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{
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int rc;
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ndev->mw_count = XEON_MW_COUNT;
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ndev->spad_count = GEN3_SPAD_COUNT;
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ndev->db_count = GEN3_DB_COUNT;
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ndev->db_link_mask = GEN3_DB_LINK_BIT;
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/* DB fixup for using 31 right now */
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if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD)
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ndev->db_link_mask |= BIT_ULL(31);
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switch (ndev->ntb.topo) {
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case NTB_TOPO_B2B_USD:
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case NTB_TOPO_B2B_DSD:
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ndev->self_reg = &gen3_pri_reg;
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ndev->peer_reg = &gen3_b2b_reg;
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ndev->xlat_reg = &gen3_sec_xlat;
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if (ndev->ntb.topo == NTB_TOPO_B2B_USD) {
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rc = gen3_setup_b2b_mw(ndev,
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&xeon_b2b_dsd_addr,
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&xeon_b2b_usd_addr);
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} else {
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rc = gen3_setup_b2b_mw(ndev,
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&xeon_b2b_usd_addr,
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&xeon_b2b_dsd_addr);
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}
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if (rc)
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return rc;
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/* Enable Bus Master and Memory Space on the secondary side */
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iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
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ndev->self_mmio + GEN3_SPCICMD_OFFSET);
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break;
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default:
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return -EINVAL;
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}
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ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
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ndev->reg->db_iowrite(ndev->db_valid_mask,
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ndev->self_mmio +
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ndev->self_reg->db_mask);
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return 0;
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}
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int gen3_init_dev(struct intel_ntb_dev *ndev)
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{
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struct pci_dev *pdev;
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u8 ppd;
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int rc;
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pdev = ndev->ntb.pdev;
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ndev->reg = &gen3_reg;
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rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd);
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if (rc)
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return -EIO;
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ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);
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dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd,
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ntb_topo_string(ndev->ntb.topo));
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if (ndev->ntb.topo == NTB_TOPO_NONE)
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return -EINVAL;
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ndev->hwerr_flags |= NTB_HWERR_MSIX_VECTOR32_BAD;
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rc = gen3_init_ntb(ndev);
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if (rc)
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return rc;
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return gen3_init_isr(ndev);
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}
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ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
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size_t count, loff_t *offp)
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{
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struct intel_ntb_dev *ndev;
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void __iomem *mmio;
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char *buf;
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size_t buf_size;
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ssize_t ret, off;
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union { u64 v64; u32 v32; u16 v16; } u;
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ndev = filp->private_data;
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mmio = ndev->self_mmio;
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buf_size = min(count, 0x800ul);
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buf = kmalloc(buf_size, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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off = 0;
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off += scnprintf(buf + off, buf_size - off,
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"NTB Device Information:\n");
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off += scnprintf(buf + off, buf_size - off,
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"Connection Topology -\t%s\n",
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ntb_topo_string(ndev->ntb.topo));
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off += scnprintf(buf + off, buf_size - off,
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"NTB CTL -\t\t%#06x\n", ndev->ntb_ctl);
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off += scnprintf(buf + off, buf_size - off,
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"LNK STA -\t\t%#06x\n", ndev->lnk_sta);
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if (!ndev->reg->link_is_up(ndev))
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off += scnprintf(buf + off, buf_size - off,
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"Link Status -\t\tDown\n");
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else {
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off += scnprintf(buf + off, buf_size - off,
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"Link Status -\t\tUp\n");
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off += scnprintf(buf + off, buf_size - off,
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"Link Speed -\t\tPCI-E Gen %u\n",
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NTB_LNK_STA_SPEED(ndev->lnk_sta));
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off += scnprintf(buf + off, buf_size - off,
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"Link Width -\t\tx%u\n",
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NTB_LNK_STA_WIDTH(ndev->lnk_sta));
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}
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off += scnprintf(buf + off, buf_size - off,
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"Memory Window Count -\t%u\n", ndev->mw_count);
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off += scnprintf(buf + off, buf_size - off,
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"Scratchpad Count -\t%u\n", ndev->spad_count);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Count -\t%u\n", ndev->db_count);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Vector Count -\t%u\n", ndev->db_vec_count);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Mask Cached -\t%#llx\n", ndev->db_mask);
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u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Mask -\t\t%#llx\n", u.v64);
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u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_bell);
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off += scnprintf(buf + off, buf_size - off,
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"Doorbell Bell -\t\t%#llx\n", u.v64);
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Incoming XLAT:\n");
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u.v64 = ioread64(mmio + GEN3_IMBAR1XBASE_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IMBAR1XBASE -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + GEN3_IMBAR2XBASE_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IMBAR2XBASE -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IMBAR1XLMT -\t\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IMBAR2XLMT -\t\t\t%#018llx\n", u.v64);
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if (ntb_topo_is_b2b(ndev->ntb.topo)) {
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Outgoing B2B XLAT:\n");
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u.v64 = ioread64(mmio + GEN3_EMBAR1XBASE_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR1XBASE -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + GEN3_EMBAR2XBASE_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR2XBASE -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + GEN3_EMBAR1XLMT_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR1XLMT -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + GEN3_EMBAR2XLMT_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR2XLMT -\t\t%#018llx\n", u.v64);
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Secondary BAR:\n");
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u.v64 = ioread64(mmio + GEN3_EMBAR0_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR0 -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + GEN3_EMBAR1_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR1 -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + GEN3_EMBAR2_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR2 -\t\t%#018llx\n", u.v64);
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}
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Statistics:\n");
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u.v16 = ioread16(mmio + GEN3_USMEMMISS_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"Upstream Memory Miss -\t%u\n", u.v16);
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Hardware Errors:\n");
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if (!pci_read_config_word(ndev->ntb.pdev,
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GEN3_DEVSTS_OFFSET, &u.v16))
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off += scnprintf(buf + off, buf_size - off,
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"DEVSTS -\t\t%#06x\n", u.v16);
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if (!pci_read_config_word(ndev->ntb.pdev,
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GEN3_LINK_STATUS_OFFSET, &u.v16))
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off += scnprintf(buf + off, buf_size - off,
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"LNKSTS -\t\t%#06x\n", u.v16);
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if (!pci_read_config_dword(ndev->ntb.pdev,
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GEN3_UNCERRSTS_OFFSET, &u.v32))
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off += scnprintf(buf + off, buf_size - off,
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"UNCERRSTS -\t\t%#06x\n", u.v32);
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if (!pci_read_config_dword(ndev->ntb.pdev,
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GEN3_CORERRSTS_OFFSET, &u.v32))
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off += scnprintf(buf + off, buf_size - off,
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"CORERRSTS -\t\t%#06x\n", u.v32);
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ret = simple_read_from_buffer(ubuf, count, offp, buf, off);
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kfree(buf);
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return ret;
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}
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int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed,
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enum ntb_width max_width)
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{
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struct intel_ntb_dev *ndev;
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u32 ntb_ctl;
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ndev = container_of(ntb, struct intel_ntb_dev, ntb);
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dev_dbg(&ntb->pdev->dev,
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"Enabling link with max_speed %d max_width %d\n",
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max_speed, max_width);
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if (max_speed != NTB_SPEED_AUTO)
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dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed);
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if (max_width != NTB_WIDTH_AUTO)
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dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width);
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ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
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ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);
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ntb_ctl |= NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP;
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ntb_ctl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP;
|
|
iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);
|
|
|
|
return 0;
|
|
}
|
|
static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
|
|
dma_addr_t addr, resource_size_t size)
|
|
{
|
|
struct intel_ntb_dev *ndev = ntb_ndev(ntb);
|
|
unsigned long xlat_reg, limit_reg;
|
|
resource_size_t bar_size, mw_size;
|
|
void __iomem *mmio;
|
|
u64 base, limit, reg_val;
|
|
int bar;
|
|
|
|
if (pidx != NTB_DEF_PEER_IDX)
|
|
return -EINVAL;
|
|
|
|
if (idx >= ndev->b2b_idx && !ndev->b2b_off)
|
|
idx += 1;
|
|
|
|
bar = ndev_mw_to_bar(ndev, idx);
|
|
if (bar < 0)
|
|
return bar;
|
|
|
|
bar_size = pci_resource_len(ndev->ntb.pdev, bar);
|
|
|
|
if (idx == ndev->b2b_idx)
|
|
mw_size = bar_size - ndev->b2b_off;
|
|
else
|
|
mw_size = bar_size;
|
|
|
|
/* hardware requires that addr is aligned to bar size */
|
|
if (addr & (bar_size - 1))
|
|
return -EINVAL;
|
|
|
|
/* make sure the range fits in the usable mw size */
|
|
if (size > mw_size)
|
|
return -EINVAL;
|
|
|
|
mmio = ndev->self_mmio;
|
|
xlat_reg = ndev->xlat_reg->bar2_xlat + (idx * 0x10);
|
|
limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10);
|
|
base = pci_resource_start(ndev->ntb.pdev, bar);
|
|
|
|
/* Set the limit if supported, if size is not mw_size */
|
|
if (limit_reg && size != mw_size)
|
|
limit = base + size;
|
|
else
|
|
limit = base + mw_size;
|
|
|
|
/* set and verify setting the translation address */
|
|
iowrite64(addr, mmio + xlat_reg);
|
|
reg_val = ioread64(mmio + xlat_reg);
|
|
if (reg_val != addr) {
|
|
iowrite64(0, mmio + xlat_reg);
|
|
return -EIO;
|
|
}
|
|
|
|
dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val);
|
|
|
|
/* set and verify setting the limit */
|
|
iowrite64(limit, mmio + limit_reg);
|
|
reg_val = ioread64(mmio + limit_reg);
|
|
if (reg_val != limit) {
|
|
iowrite64(base, mmio + limit_reg);
|
|
iowrite64(0, mmio + xlat_reg);
|
|
return -EIO;
|
|
}
|
|
|
|
dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val);
|
|
|
|
/* setup the EP */
|
|
limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10) + 0x4000;
|
|
base = ioread64(mmio + GEN3_EMBAR1_OFFSET + (8 * idx));
|
|
base &= ~0xf;
|
|
|
|
if (limit_reg && size != mw_size)
|
|
limit = base + size;
|
|
else
|
|
limit = base + mw_size;
|
|
|
|
/* set and verify setting the limit */
|
|
iowrite64(limit, mmio + limit_reg);
|
|
reg_val = ioread64(mmio + limit_reg);
|
|
if (reg_val != limit) {
|
|
iowrite64(base, mmio + limit_reg);
|
|
iowrite64(0, mmio + xlat_reg);
|
|
return -EIO;
|
|
}
|
|
|
|
dev_dbg(&ntb->pdev->dev, "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
|
|
resource_size_t *db_size,
|
|
u64 *db_data, int db_bit)
|
|
{
|
|
phys_addr_t db_addr_base;
|
|
struct intel_ntb_dev *ndev = ntb_ndev(ntb);
|
|
|
|
if (unlikely(db_bit >= BITS_PER_LONG_LONG))
|
|
return -EINVAL;
|
|
|
|
if (unlikely(BIT_ULL(db_bit) & ~ntb_ndev(ntb)->db_valid_mask))
|
|
return -EINVAL;
|
|
|
|
ndev_db_addr(ndev, &db_addr_base, db_size, ndev->peer_addr,
|
|
ndev->peer_reg->db_bell);
|
|
|
|
if (db_addr) {
|
|
*db_addr = db_addr_base + (db_bit * 4);
|
|
dev_dbg(&ndev->ntb.pdev->dev, "Peer db addr %llx db bit %d\n",
|
|
*db_addr, db_bit);
|
|
}
|
|
|
|
if (db_data) {
|
|
*db_data = 1;
|
|
dev_dbg(&ndev->ntb.pdev->dev, "Peer db data %llx db bit %d\n",
|
|
*db_data, db_bit);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits)
|
|
{
|
|
struct intel_ntb_dev *ndev = ntb_ndev(ntb);
|
|
int bit;
|
|
|
|
if (db_bits & ~ndev->db_valid_mask)
|
|
return -EINVAL;
|
|
|
|
while (db_bits) {
|
|
bit = __ffs(db_bits);
|
|
iowrite32(1, ndev->peer_mmio +
|
|
ndev->peer_reg->db_bell + (bit * 4));
|
|
db_bits &= db_bits - 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
u64 intel_ntb3_db_read(struct ntb_dev *ntb)
|
|
{
|
|
struct intel_ntb_dev *ndev = ntb_ndev(ntb);
|
|
|
|
return ndev_db_read(ndev,
|
|
ndev->self_mmio +
|
|
ndev->self_reg->db_clear);
|
|
}
|
|
|
|
int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits)
|
|
{
|
|
struct intel_ntb_dev *ndev = ntb_ndev(ntb);
|
|
|
|
return ndev_db_write(ndev, db_bits,
|
|
ndev->self_mmio +
|
|
ndev->self_reg->db_clear);
|
|
}
|
|
|
|
const struct ntb_dev_ops intel_ntb3_ops = {
|
|
.mw_count = intel_ntb_mw_count,
|
|
.mw_get_align = intel_ntb_mw_get_align,
|
|
.mw_set_trans = intel_ntb3_mw_set_trans,
|
|
.peer_mw_count = intel_ntb_peer_mw_count,
|
|
.peer_mw_get_addr = intel_ntb_peer_mw_get_addr,
|
|
.link_is_up = intel_ntb_link_is_up,
|
|
.link_enable = intel_ntb3_link_enable,
|
|
.link_disable = intel_ntb_link_disable,
|
|
.db_valid_mask = intel_ntb_db_valid_mask,
|
|
.db_vector_count = intel_ntb_db_vector_count,
|
|
.db_vector_mask = intel_ntb_db_vector_mask,
|
|
.db_read = intel_ntb3_db_read,
|
|
.db_clear = intel_ntb3_db_clear,
|
|
.db_set_mask = intel_ntb_db_set_mask,
|
|
.db_clear_mask = intel_ntb_db_clear_mask,
|
|
.peer_db_addr = intel_ntb3_peer_db_addr,
|
|
.peer_db_set = intel_ntb3_peer_db_set,
|
|
.spad_is_unsafe = intel_ntb_spad_is_unsafe,
|
|
.spad_count = intel_ntb_spad_count,
|
|
.spad_read = intel_ntb_spad_read,
|
|
.spad_write = intel_ntb_spad_write,
|
|
.peer_spad_addr = intel_ntb_peer_spad_addr,
|
|
.peer_spad_read = intel_ntb_peer_spad_read,
|
|
.peer_spad_write = intel_ntb_peer_spad_write,
|
|
};
|
|
|