596 lines
15 KiB
C
596 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Real Time Clock driver for AB-RTCMC-32.768kHz-EOZ9 chip.
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* Copyright (C) 2019 Orolia
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*
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*/
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#include <linux/module.h>
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#include <linux/rtc.h>
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#include <linux/i2c.h>
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#include <linux/bcd.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/bitfield.h>
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#include <linux/hwmon.h>
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#include <linux/hwmon-sysfs.h>
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#define ABEOZ9_REG_CTRL1 0x00
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#define ABEOZ9_REG_CTRL1_MASK GENMASK(7, 0)
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#define ABEOZ9_REG_CTRL1_WE BIT(0)
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#define ABEOZ9_REG_CTRL1_TE BIT(1)
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#define ABEOZ9_REG_CTRL1_TAR BIT(2)
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#define ABEOZ9_REG_CTRL1_EERE BIT(3)
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#define ABEOZ9_REG_CTRL1_SRON BIT(4)
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#define ABEOZ9_REG_CTRL1_TD0 BIT(5)
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#define ABEOZ9_REG_CTRL1_TD1 BIT(6)
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#define ABEOZ9_REG_CTRL1_CLKINT BIT(7)
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#define ABEOZ9_REG_CTRL_INT 0x01
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#define ABEOZ9_REG_CTRL_INT_AIE BIT(0)
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#define ABEOZ9_REG_CTRL_INT_TIE BIT(1)
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#define ABEOZ9_REG_CTRL_INT_V1IE BIT(2)
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#define ABEOZ9_REG_CTRL_INT_V2IE BIT(3)
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#define ABEOZ9_REG_CTRL_INT_SRIE BIT(4)
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#define ABEOZ9_REG_CTRL_INT_FLAG 0x02
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#define ABEOZ9_REG_CTRL_INT_FLAG_AF BIT(0)
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#define ABEOZ9_REG_CTRL_INT_FLAG_TF BIT(1)
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#define ABEOZ9_REG_CTRL_INT_FLAG_V1IF BIT(2)
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#define ABEOZ9_REG_CTRL_INT_FLAG_V2IF BIT(3)
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#define ABEOZ9_REG_CTRL_INT_FLAG_SRF BIT(4)
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#define ABEOZ9_REG_CTRL_STATUS 0x03
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#define ABEOZ9_REG_CTRL_STATUS_V1F BIT(2)
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#define ABEOZ9_REG_CTRL_STATUS_V2F BIT(3)
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#define ABEOZ9_REG_CTRL_STATUS_SR BIT(4)
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#define ABEOZ9_REG_CTRL_STATUS_PON BIT(5)
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#define ABEOZ9_REG_CTRL_STATUS_EEBUSY BIT(7)
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#define ABEOZ9_REG_SEC 0x08
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#define ABEOZ9_REG_MIN 0x09
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#define ABEOZ9_REG_HOURS 0x0A
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#define ABEOZ9_HOURS_PM BIT(6)
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#define ABEOZ9_REG_DAYS 0x0B
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#define ABEOZ9_REG_WEEKDAYS 0x0C
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#define ABEOZ9_REG_MONTHS 0x0D
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#define ABEOZ9_REG_YEARS 0x0E
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#define ABEOZ9_SEC_LEN 7
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#define ABEOZ9_REG_ALARM_SEC 0x10
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#define ABEOZ9_BIT_ALARM_SEC GENMASK(6, 0)
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#define ABEOZ9_REG_ALARM_MIN 0x11
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#define ABEOZ9_BIT_ALARM_MIN GENMASK(6, 0)
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#define ABEOZ9_REG_ALARM_HOURS 0x12
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#define ABEOZ9_BIT_ALARM_HOURS_PM BIT(5)
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#define ABEOZ9_BIT_ALARM_HOURS GENMASK(4, 0)
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#define ABEOZ9_REG_ALARM_DAYS 0x13
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#define ABEOZ9_BIT_ALARM_DAYS GENMASK(5, 0)
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#define ABEOZ9_REG_ALARM_WEEKDAYS 0x14
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#define ABEOZ9_BIT_ALARM_WEEKDAYS GENMASK(2, 0)
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#define ABEOZ9_REG_ALARM_MONTHS 0x15
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#define ABEOZ9_BIT_ALARM_MONTHS GENMASK(4, 0)
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#define ABEOZ9_REG_ALARM_YEARS 0x16
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#define ABEOZ9_ALARM_LEN 7
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#define ABEOZ9_BIT_ALARM_AE BIT(7)
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#define ABEOZ9_REG_REG_TEMP 0x20
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#define ABEOZ953_TEMP_MAX 120
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#define ABEOZ953_TEMP_MIN -60
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#define ABEOZ9_REG_EEPROM 0x30
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#define ABEOZ9_REG_EEPROM_MASK GENMASK(8, 0)
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#define ABEOZ9_REG_EEPROM_THP BIT(0)
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#define ABEOZ9_REG_EEPROM_THE BIT(1)
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#define ABEOZ9_REG_EEPROM_FD0 BIT(2)
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#define ABEOZ9_REG_EEPROM_FD1 BIT(3)
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#define ABEOZ9_REG_EEPROM_R1K BIT(4)
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#define ABEOZ9_REG_EEPROM_R5K BIT(5)
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#define ABEOZ9_REG_EEPROM_R20K BIT(6)
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#define ABEOZ9_REG_EEPROM_R80K BIT(7)
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struct abeoz9_rtc_data {
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struct rtc_device *rtc;
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struct regmap *regmap;
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struct device *hwmon_dev;
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};
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static int abeoz9_check_validity(struct device *dev)
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{
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struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
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struct regmap *regmap = data->regmap;
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int ret;
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int val;
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ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val);
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if (ret < 0) {
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dev_err(dev,
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"unable to get CTRL_STATUS register (%d)\n", ret);
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return ret;
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}
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if (val & ABEOZ9_REG_CTRL_STATUS_PON) {
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dev_warn(dev, "power-on reset detected, date is invalid\n");
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return -EINVAL;
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}
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if (val & ABEOZ9_REG_CTRL_STATUS_V1F) {
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dev_warn(dev,
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"voltage drops below VLOW1 threshold, date is invalid\n");
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return -EINVAL;
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}
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if ((val & ABEOZ9_REG_CTRL_STATUS_V2F)) {
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dev_warn(dev,
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"voltage drops below VLOW2 threshold, date is invalid\n");
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return -EINVAL;
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}
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return 0;
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}
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static int abeoz9_reset_validity(struct regmap *regmap)
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{
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return regmap_update_bits(regmap, ABEOZ9_REG_CTRL_STATUS,
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ABEOZ9_REG_CTRL_STATUS_V1F |
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ABEOZ9_REG_CTRL_STATUS_V2F |
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ABEOZ9_REG_CTRL_STATUS_PON,
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0);
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}
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static int abeoz9_rtc_get_time(struct device *dev, struct rtc_time *tm)
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{
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struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
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u8 regs[ABEOZ9_SEC_LEN];
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int ret;
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ret = abeoz9_check_validity(dev);
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if (ret)
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return ret;
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ret = regmap_bulk_read(data->regmap, ABEOZ9_REG_SEC,
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regs,
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sizeof(regs));
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if (ret) {
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dev_err(dev, "reading RTC time failed (%d)\n", ret);
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return ret;
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}
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tm->tm_sec = bcd2bin(regs[ABEOZ9_REG_SEC - ABEOZ9_REG_SEC] & 0x7F);
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tm->tm_min = bcd2bin(regs[ABEOZ9_REG_MIN - ABEOZ9_REG_SEC] & 0x7F);
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if (regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & ABEOZ9_HOURS_PM) {
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tm->tm_hour =
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bcd2bin(regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & 0x1f);
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if (regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & ABEOZ9_HOURS_PM)
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tm->tm_hour += 12;
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} else {
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tm->tm_hour = bcd2bin(regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC]);
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}
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tm->tm_mday = bcd2bin(regs[ABEOZ9_REG_DAYS - ABEOZ9_REG_SEC]);
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tm->tm_wday = bcd2bin(regs[ABEOZ9_REG_WEEKDAYS - ABEOZ9_REG_SEC]);
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tm->tm_mon = bcd2bin(regs[ABEOZ9_REG_MONTHS - ABEOZ9_REG_SEC]) - 1;
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tm->tm_year = bcd2bin(regs[ABEOZ9_REG_YEARS - ABEOZ9_REG_SEC]) + 100;
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return ret;
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}
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static int abeoz9_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
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struct regmap *regmap = data->regmap;
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u8 regs[ABEOZ9_SEC_LEN];
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int ret;
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regs[ABEOZ9_REG_SEC - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_sec);
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regs[ABEOZ9_REG_MIN - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_min);
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regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_hour);
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regs[ABEOZ9_REG_DAYS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_mday);
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regs[ABEOZ9_REG_WEEKDAYS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_wday);
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regs[ABEOZ9_REG_MONTHS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_mon + 1);
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regs[ABEOZ9_REG_YEARS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_year - 100);
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ret = regmap_bulk_write(data->regmap, ABEOZ9_REG_SEC,
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regs,
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sizeof(regs));
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if (ret) {
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dev_err(dev, "set RTC time failed (%d)\n", ret);
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return ret;
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}
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return abeoz9_reset_validity(regmap);
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}
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static int abeoz9_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
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struct regmap *regmap = data->regmap;
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u8 regs[ABEOZ9_ALARM_LEN];
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u8 val[2];
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int ret;
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ret = abeoz9_check_validity(dev);
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if (ret)
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return ret;
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ret = regmap_bulk_read(regmap, ABEOZ9_REG_CTRL_INT, val, sizeof(val));
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if (ret)
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return ret;
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alarm->enabled = val[0] & ABEOZ9_REG_CTRL_INT_AIE;
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alarm->pending = val[1] & ABEOZ9_REG_CTRL_INT_FLAG_AF;
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ret = regmap_bulk_read(regmap, ABEOZ9_REG_ALARM_SEC, regs, sizeof(regs));
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if (ret)
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return ret;
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alarm->time.tm_sec = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_SEC, regs[0]));
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alarm->time.tm_min = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_MIN, regs[1]));
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alarm->time.tm_hour = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_HOURS, regs[2]));
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if (FIELD_GET(ABEOZ9_BIT_ALARM_HOURS_PM, regs[2]))
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alarm->time.tm_hour += 12;
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alarm->time.tm_mday = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_DAYS, regs[3]));
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return 0;
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}
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static int abeoz9_rtc_alarm_irq_enable(struct device *dev, u32 enable)
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{
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struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
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return regmap_update_bits(data->regmap, ABEOZ9_REG_CTRL_INT,
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ABEOZ9_REG_CTRL_INT_AIE,
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FIELD_PREP(ABEOZ9_REG_CTRL_INT_AIE, enable));
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}
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static int abeoz9_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
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u8 regs[ABEOZ9_ALARM_LEN] = {0};
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int ret;
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ret = regmap_update_bits(data->regmap, ABEOZ9_REG_CTRL_INT_FLAG,
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ABEOZ9_REG_CTRL_INT_FLAG_AF, 0);
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if (ret)
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return ret;
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regs[0] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_SEC,
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bin2bcd(alarm->time.tm_sec));
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regs[1] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_MIN,
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bin2bcd(alarm->time.tm_min));
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regs[2] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_HOURS,
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bin2bcd(alarm->time.tm_hour));
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regs[3] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_DAYS,
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bin2bcd(alarm->time.tm_mday));
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ret = regmap_bulk_write(data->regmap, ABEOZ9_REG_ALARM_SEC, regs,
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sizeof(regs));
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if (ret)
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return ret;
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return abeoz9_rtc_alarm_irq_enable(dev, alarm->enabled);
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}
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static irqreturn_t abeoz9_rtc_irq(int irq, void *dev)
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{
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struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
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unsigned int val;
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int ret;
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ret = regmap_read(data->regmap, ABEOZ9_REG_CTRL_INT_FLAG, &val);
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if (ret)
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return IRQ_NONE;
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if (!FIELD_GET(ABEOZ9_REG_CTRL_INT_FLAG_AF, val))
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return IRQ_NONE;
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regmap_update_bits(data->regmap, ABEOZ9_REG_CTRL_INT_FLAG,
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ABEOZ9_REG_CTRL_INT_FLAG_AF, 0);
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rtc_update_irq(data->rtc, 1, RTC_IRQF | RTC_AF);
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return IRQ_HANDLED;
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}
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static int abeoz9_trickle_parse_dt(struct device_node *node)
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{
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u32 ohms = 0;
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if (of_property_read_u32(node, "trickle-resistor-ohms", &ohms))
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return 0;
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switch (ohms) {
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case 1000:
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return ABEOZ9_REG_EEPROM_R1K;
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case 5000:
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return ABEOZ9_REG_EEPROM_R5K;
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case 20000:
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return ABEOZ9_REG_EEPROM_R20K;
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case 80000:
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return ABEOZ9_REG_EEPROM_R80K;
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default:
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return 0;
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}
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}
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static int abeoz9_rtc_setup(struct device *dev, struct device_node *node)
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{
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struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
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struct regmap *regmap = data->regmap;
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int ret;
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/* Enable Self Recovery, Clock for Watch and EEPROM refresh functions */
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ret = regmap_update_bits(regmap, ABEOZ9_REG_CTRL1,
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ABEOZ9_REG_CTRL1_MASK,
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ABEOZ9_REG_CTRL1_WE |
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ABEOZ9_REG_CTRL1_EERE |
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ABEOZ9_REG_CTRL1_SRON);
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if (ret < 0) {
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dev_err(dev, "unable to set CTRL_1 register (%d)\n", ret);
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return ret;
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}
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ret = regmap_write(regmap, ABEOZ9_REG_CTRL_INT, 0);
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if (ret < 0) {
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dev_err(dev,
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"unable to set control CTRL_INT register (%d)\n",
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ret);
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return ret;
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}
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ret = regmap_write(regmap, ABEOZ9_REG_CTRL_INT_FLAG, 0);
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if (ret < 0) {
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dev_err(dev,
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"unable to set control CTRL_INT_FLAG register (%d)\n",
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ret);
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return ret;
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}
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ret = abeoz9_trickle_parse_dt(node);
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/* Enable built-in termometer */
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ret |= ABEOZ9_REG_EEPROM_THE;
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ret = regmap_update_bits(regmap, ABEOZ9_REG_EEPROM,
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ABEOZ9_REG_EEPROM_MASK,
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ret);
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if (ret < 0) {
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dev_err(dev, "unable to set EEPROM register (%d)\n", ret);
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return ret;
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}
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return ret;
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}
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static const struct rtc_class_ops rtc_ops = {
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.read_time = abeoz9_rtc_get_time,
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.set_time = abeoz9_rtc_set_time,
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.read_alarm = abeoz9_rtc_read_alarm,
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.set_alarm = abeoz9_rtc_set_alarm,
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.alarm_irq_enable = abeoz9_rtc_alarm_irq_enable,
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};
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static const struct regmap_config abeoz9_rtc_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = 0x3f,
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};
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#if IS_REACHABLE(CONFIG_HWMON)
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static int abeoz9z3_temp_read(struct device *dev,
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enum hwmon_sensor_types type,
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u32 attr, int channel, long *temp)
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{
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struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
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struct regmap *regmap = data->regmap;
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int ret;
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unsigned int val;
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ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val);
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if (ret < 0)
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return ret;
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if ((val & ABEOZ9_REG_CTRL_STATUS_V1F) ||
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(val & ABEOZ9_REG_CTRL_STATUS_V2F)) {
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dev_err(dev,
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"thermometer might be disabled due to low voltage\n");
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return -EINVAL;
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}
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switch (attr) {
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case hwmon_temp_input:
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ret = regmap_read(regmap, ABEOZ9_REG_REG_TEMP, &val);
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if (ret < 0)
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return ret;
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*temp = 1000 * (val + ABEOZ953_TEMP_MIN);
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return 0;
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case hwmon_temp_max:
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*temp = 1000 * ABEOZ953_TEMP_MAX;
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return 0;
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case hwmon_temp_min:
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*temp = 1000 * ABEOZ953_TEMP_MIN;
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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}
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static umode_t abeoz9_is_visible(const void *data,
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enum hwmon_sensor_types type,
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|
u32 attr, int channel)
|
|
{
|
|
switch (attr) {
|
|
case hwmon_temp_input:
|
|
case hwmon_temp_max:
|
|
case hwmon_temp_min:
|
|
return 0444;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static const u32 abeoz9_chip_config[] = {
|
|
HWMON_C_REGISTER_TZ,
|
|
0
|
|
};
|
|
|
|
static const struct hwmon_channel_info abeoz9_chip = {
|
|
.type = hwmon_chip,
|
|
.config = abeoz9_chip_config,
|
|
};
|
|
|
|
static const u32 abeoz9_temp_config[] = {
|
|
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN,
|
|
0
|
|
};
|
|
|
|
static const struct hwmon_channel_info abeoz9_temp = {
|
|
.type = hwmon_temp,
|
|
.config = abeoz9_temp_config,
|
|
};
|
|
|
|
static const struct hwmon_channel_info *abeoz9_info[] = {
|
|
&abeoz9_chip,
|
|
&abeoz9_temp,
|
|
NULL
|
|
};
|
|
|
|
static const struct hwmon_ops abeoz9_hwmon_ops = {
|
|
.is_visible = abeoz9_is_visible,
|
|
.read = abeoz9z3_temp_read,
|
|
};
|
|
|
|
static const struct hwmon_chip_info abeoz9_chip_info = {
|
|
.ops = &abeoz9_hwmon_ops,
|
|
.info = abeoz9_info,
|
|
};
|
|
|
|
static void abeoz9_hwmon_register(struct device *dev,
|
|
struct abeoz9_rtc_data *data)
|
|
{
|
|
data->hwmon_dev =
|
|
devm_hwmon_device_register_with_info(dev,
|
|
"abeoz9",
|
|
data,
|
|
&abeoz9_chip_info,
|
|
NULL);
|
|
if (IS_ERR(data->hwmon_dev)) {
|
|
dev_warn(dev, "unable to register hwmon device %ld\n",
|
|
PTR_ERR(data->hwmon_dev));
|
|
}
|
|
}
|
|
|
|
#else
|
|
|
|
static void abeoz9_hwmon_register(struct device *dev,
|
|
struct abeoz9_rtc_data *data)
|
|
{
|
|
}
|
|
|
|
#endif
|
|
|
|
static int abeoz9_probe(struct i2c_client *client)
|
|
{
|
|
struct abeoz9_rtc_data *data = NULL;
|
|
struct device *dev = &client->dev;
|
|
struct regmap *regmap;
|
|
int ret;
|
|
|
|
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
|
|
I2C_FUNC_SMBUS_BYTE_DATA |
|
|
I2C_FUNC_SMBUS_I2C_BLOCK))
|
|
return -ENODEV;
|
|
|
|
regmap = devm_regmap_init_i2c(client, &abeoz9_rtc_regmap_config);
|
|
if (IS_ERR(regmap)) {
|
|
ret = PTR_ERR(regmap);
|
|
dev_err(dev, "regmap allocation failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
data->regmap = regmap;
|
|
dev_set_drvdata(dev, data);
|
|
|
|
ret = abeoz9_rtc_setup(dev, client->dev.of_node);
|
|
if (ret)
|
|
return ret;
|
|
|
|
data->rtc = devm_rtc_allocate_device(dev);
|
|
ret = PTR_ERR_OR_ZERO(data->rtc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
data->rtc->ops = &rtc_ops;
|
|
data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
|
|
data->rtc->range_max = RTC_TIMESTAMP_END_2099;
|
|
clear_bit(RTC_FEATURE_ALARM, data->rtc->features);
|
|
|
|
if (client->irq > 0) {
|
|
unsigned long irqflags = IRQF_TRIGGER_LOW;
|
|
|
|
if (dev_fwnode(&client->dev))
|
|
irqflags = 0;
|
|
|
|
ret = devm_request_threaded_irq(dev, client->irq, NULL,
|
|
abeoz9_rtc_irq,
|
|
irqflags | IRQF_ONESHOT,
|
|
dev_name(dev), dev);
|
|
if (ret) {
|
|
dev_err(dev, "failed to request alarm irq\n");
|
|
return ret;
|
|
}
|
|
} else {
|
|
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, data->rtc->features);
|
|
}
|
|
|
|
if (client->irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
|
|
ret = device_init_wakeup(dev, true);
|
|
set_bit(RTC_FEATURE_ALARM, data->rtc->features);
|
|
}
|
|
|
|
ret = devm_rtc_register_device(data->rtc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
abeoz9_hwmon_register(dev, data);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id abeoz9_dt_match[] = {
|
|
{ .compatible = "abracon,abeoz9" },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, abeoz9_dt_match);
|
|
#endif
|
|
|
|
static const struct i2c_device_id abeoz9_id[] = {
|
|
{ "abeoz9", 0 },
|
|
{ }
|
|
};
|
|
|
|
static struct i2c_driver abeoz9_driver = {
|
|
.driver = {
|
|
.name = "rtc-ab-eoz9",
|
|
.of_match_table = of_match_ptr(abeoz9_dt_match),
|
|
},
|
|
.probe_new = abeoz9_probe,
|
|
.id_table = abeoz9_id,
|
|
};
|
|
|
|
module_i2c_driver(abeoz9_driver);
|
|
|
|
MODULE_AUTHOR("Artem Panfilov <panfilov.artyom@gmail.com>");
|
|
MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-EOZ9 RTC driver");
|
|
MODULE_LICENSE("GPL");
|