592 lines
15 KiB
C
592 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* RTC driver for the Armada 38x Marvell SoCs
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*
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* Copyright (C) 2015 Marvell
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*
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* Gregory Clement <gregory.clement@free-electrons.com>
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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#define RTC_STATUS 0x0
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#define RTC_STATUS_ALARM1 BIT(0)
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#define RTC_STATUS_ALARM2 BIT(1)
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#define RTC_IRQ1_CONF 0x4
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#define RTC_IRQ2_CONF 0x8
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#define RTC_IRQ_AL_EN BIT(0)
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#define RTC_IRQ_FREQ_EN BIT(1)
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#define RTC_IRQ_FREQ_1HZ BIT(2)
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#define RTC_CCR 0x18
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#define RTC_CCR_MODE BIT(15)
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#define RTC_CONF_TEST 0x1C
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#define RTC_NOMINAL_TIMING BIT(13)
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#define RTC_TIME 0xC
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#define RTC_ALARM1 0x10
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#define RTC_ALARM2 0x14
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/* Armada38x SoC registers */
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#define RTC_38X_BRIDGE_TIMING_CTL 0x0
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#define RTC_38X_PERIOD_OFFS 0
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#define RTC_38X_PERIOD_MASK (0x3FF << RTC_38X_PERIOD_OFFS)
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#define RTC_38X_READ_DELAY_OFFS 26
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#define RTC_38X_READ_DELAY_MASK (0x1F << RTC_38X_READ_DELAY_OFFS)
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/* Armada 7K/8K registers */
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#define RTC_8K_BRIDGE_TIMING_CTL0 0x0
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#define RTC_8K_WRCLK_PERIOD_OFFS 0
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#define RTC_8K_WRCLK_PERIOD_MASK (0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS)
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#define RTC_8K_WRCLK_SETUP_OFFS 16
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#define RTC_8K_WRCLK_SETUP_MASK (0xFFFF << RTC_8K_WRCLK_SETUP_OFFS)
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#define RTC_8K_BRIDGE_TIMING_CTL1 0x4
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#define RTC_8K_READ_DELAY_OFFS 0
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#define RTC_8K_READ_DELAY_MASK (0xFFFF << RTC_8K_READ_DELAY_OFFS)
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#define RTC_8K_ISR 0x10
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#define RTC_8K_IMR 0x14
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#define RTC_8K_ALARM2 BIT(0)
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#define SOC_RTC_INTERRUPT 0x8
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#define SOC_RTC_ALARM1 BIT(0)
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#define SOC_RTC_ALARM2 BIT(1)
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#define SOC_RTC_ALARM1_MASK BIT(2)
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#define SOC_RTC_ALARM2_MASK BIT(3)
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#define SAMPLE_NR 100
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struct value_to_freq {
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u32 value;
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u8 freq;
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};
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struct armada38x_rtc {
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struct rtc_device *rtc_dev;
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void __iomem *regs;
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void __iomem *regs_soc;
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spinlock_t lock;
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int irq;
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bool initialized;
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struct value_to_freq *val_to_freq;
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const struct armada38x_rtc_data *data;
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};
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#define ALARM1 0
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#define ALARM2 1
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#define ALARM_REG(base, alarm) ((base) + (alarm) * sizeof(u32))
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struct armada38x_rtc_data {
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/* Initialize the RTC-MBUS bridge timing */
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void (*update_mbus_timing)(struct armada38x_rtc *rtc);
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u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg);
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void (*clear_isr)(struct armada38x_rtc *rtc);
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void (*unmask_interrupt)(struct armada38x_rtc *rtc);
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u32 alarm;
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};
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/*
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* According to the datasheet, the OS should wait 5us after every
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* register write to the RTC hard macro so that the required update
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* can occur without holding off the system bus
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* According to errata RES-3124064, Write to any RTC register
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* may fail. As a workaround, before writing to RTC
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* register, issue a dummy write of 0x0 twice to RTC Status
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* register.
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*/
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static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
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{
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writel(0, rtc->regs + RTC_STATUS);
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writel(0, rtc->regs + RTC_STATUS);
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writel(val, rtc->regs + offset);
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udelay(5);
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}
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/* Update RTC-MBUS bridge timing parameters */
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static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
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{
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u32 reg;
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reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
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reg &= ~RTC_38X_PERIOD_MASK;
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reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */
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reg &= ~RTC_38X_READ_DELAY_MASK;
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reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */
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writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
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}
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static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc)
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{
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u32 reg;
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reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
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reg &= ~RTC_8K_WRCLK_PERIOD_MASK;
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reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS;
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reg &= ~RTC_8K_WRCLK_SETUP_MASK;
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reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS;
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writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
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reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
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reg &= ~RTC_8K_READ_DELAY_MASK;
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reg |= 0x3F << RTC_8K_READ_DELAY_OFFS;
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writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
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}
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static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg)
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{
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return readl(rtc->regs + rtc_reg);
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}
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static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
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{
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int i, index_max = 0, max = 0;
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for (i = 0; i < SAMPLE_NR; i++) {
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rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg);
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rtc->val_to_freq[i].freq = 0;
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}
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for (i = 0; i < SAMPLE_NR; i++) {
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int j = 0;
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u32 value = rtc->val_to_freq[i].value;
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while (rtc->val_to_freq[j].freq) {
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if (rtc->val_to_freq[j].value == value) {
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rtc->val_to_freq[j].freq++;
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break;
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}
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j++;
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}
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if (!rtc->val_to_freq[j].freq) {
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rtc->val_to_freq[j].value = value;
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rtc->val_to_freq[j].freq = 1;
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}
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if (rtc->val_to_freq[j].freq > max) {
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index_max = j;
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max = rtc->val_to_freq[j].freq;
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}
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/*
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* If a value already has half of the sample this is the most
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* frequent one and we can stop the research right now
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*/
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if (max > SAMPLE_NR / 2)
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break;
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}
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return rtc->val_to_freq[index_max].value;
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}
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static void armada38x_clear_isr(struct armada38x_rtc *rtc)
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{
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u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
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writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
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}
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static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
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{
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u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
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writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
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}
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static void armada8k_clear_isr(struct armada38x_rtc *rtc)
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{
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writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
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}
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static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc)
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{
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writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
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}
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static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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unsigned long time, flags;
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spin_lock_irqsave(&rtc->lock, flags);
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time = rtc->data->read_rtc_reg(rtc, RTC_TIME);
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spin_unlock_irqrestore(&rtc->lock, flags);
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rtc_time64_to_tm(time, tm);
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return 0;
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}
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static void armada38x_rtc_reset(struct armada38x_rtc *rtc)
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{
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u32 reg;
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reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST);
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/* If bits [7:0] are non-zero, assume RTC was uninitialized */
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if (reg & 0xff) {
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rtc_delayed_write(0, rtc, RTC_CONF_TEST);
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msleep(500); /* Oscillator startup time */
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rtc_delayed_write(0, rtc, RTC_TIME);
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rtc_delayed_write(SOC_RTC_ALARM1 | SOC_RTC_ALARM2, rtc,
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RTC_STATUS);
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rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CCR);
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}
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rtc->initialized = true;
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}
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static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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unsigned long time, flags;
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time = rtc_tm_to_time64(tm);
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if (!rtc->initialized)
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armada38x_rtc_reset(rtc);
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spin_lock_irqsave(&rtc->lock, flags);
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rtc_delayed_write(time, rtc, RTC_TIME);
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spin_unlock_irqrestore(&rtc->lock, flags);
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return 0;
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}
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static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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unsigned long time, flags;
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u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
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u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
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u32 val;
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spin_lock_irqsave(&rtc->lock, flags);
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time = rtc->data->read_rtc_reg(rtc, reg);
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val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN;
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spin_unlock_irqrestore(&rtc->lock, flags);
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alrm->enabled = val ? 1 : 0;
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rtc_time64_to_tm(time, &alrm->time);
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return 0;
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}
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static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
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u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
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unsigned long time, flags;
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time = rtc_tm_to_time64(&alrm->time);
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spin_lock_irqsave(&rtc->lock, flags);
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rtc_delayed_write(time, rtc, reg);
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if (alrm->enabled) {
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rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
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rtc->data->unmask_interrupt(rtc);
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}
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spin_unlock_irqrestore(&rtc->lock, flags);
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return 0;
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}
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static int armada38x_rtc_alarm_irq_enable(struct device *dev,
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unsigned int enabled)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
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unsigned long flags;
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spin_lock_irqsave(&rtc->lock, flags);
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if (enabled)
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rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
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else
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rtc_delayed_write(0, rtc, reg_irq);
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spin_unlock_irqrestore(&rtc->lock, flags);
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return 0;
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}
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static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
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{
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struct armada38x_rtc *rtc = data;
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u32 val;
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int event = RTC_IRQF | RTC_AF;
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u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
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dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
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spin_lock(&rtc->lock);
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rtc->data->clear_isr(rtc);
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val = rtc->data->read_rtc_reg(rtc, reg_irq);
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/* disable all the interrupts for alarm*/
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rtc_delayed_write(0, rtc, reg_irq);
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/* Ack the event */
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rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS);
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spin_unlock(&rtc->lock);
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if (val & RTC_IRQ_FREQ_EN) {
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if (val & RTC_IRQ_FREQ_1HZ)
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event |= RTC_UF;
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else
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event |= RTC_PF;
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}
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rtc_update_irq(rtc->rtc_dev, 1, event);
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return IRQ_HANDLED;
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}
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/*
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* The information given in the Armada 388 functional spec is complex.
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* They give two different formulas for calculating the offset value,
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* but when considering "Offset" as an 8-bit signed integer, they both
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* reduce down to (we shall rename "Offset" as "val" here):
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*
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* val = (f_ideal / f_measured - 1) / resolution where f_ideal = 32768
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*
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* Converting to time, f = 1/t:
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* val = (t_measured / t_ideal - 1) / resolution where t_ideal = 1/32768
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*
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* => t_measured / t_ideal = val * resolution + 1
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*
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* "offset" in the RTC interface is defined as:
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* t = t0 * (1 + offset * 1e-9)
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* where t is the desired period, t0 is the measured period with a zero
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* offset, which is t_measured above. With t0 = t_measured and t = t_ideal,
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* offset = (t_ideal / t_measured - 1) / 1e-9
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*
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* => t_ideal / t_measured = offset * 1e-9 + 1
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*
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* so:
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*
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* offset * 1e-9 + 1 = 1 / (val * resolution + 1)
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*
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* We want "resolution" to be an integer, so resolution = R * 1e-9, giving
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* offset = 1e18 / (val * R + 1e9) - 1e9
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* val = (1e18 / (offset + 1e9) - 1e9) / R
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* with a common transformation:
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* f(x) = 1e18 / (x + 1e9) - 1e9
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* offset = f(val * R)
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* val = f(offset) / R
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*
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* Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb).
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*/
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static long armada38x_ppb_convert(long ppb)
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{
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long div = ppb + 1000000000L;
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return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L;
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}
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static int armada38x_rtc_read_offset(struct device *dev, long *offset)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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unsigned long ccr, flags;
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long ppb_cor;
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spin_lock_irqsave(&rtc->lock, flags);
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ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR);
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spin_unlock_irqrestore(&rtc->lock, flags);
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ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr;
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/* ppb_cor + 1000000000L can never be zero */
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*offset = armada38x_ppb_convert(ppb_cor);
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return 0;
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}
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static int armada38x_rtc_set_offset(struct device *dev, long offset)
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{
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struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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unsigned long ccr = 0;
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long ppb_cor, off;
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/*
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* The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we
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* need to clamp the input. This equates to -484270 .. 488558.
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* Not only is this to stop out of range "off" but also to
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* avoid the division by zero in armada38x_ppb_convert().
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*/
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offset = clamp(offset, -484270L, 488558L);
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ppb_cor = armada38x_ppb_convert(offset);
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/*
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* Use low update mode where possible, which gives a better
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* resolution of correction.
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*/
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off = DIV_ROUND_CLOSEST(ppb_cor, 954);
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if (off > 127 || off < -128) {
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ccr = RTC_CCR_MODE;
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off = DIV_ROUND_CLOSEST(ppb_cor, 3815);
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}
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/*
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* Armada 388 requires a bit pattern in bits 14..8 depending on
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* the sign bit: { 0, ~S, S, S, S, S, S }
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*/
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ccr |= (off & 0x3fff) ^ 0x2000;
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rtc_delayed_write(ccr, rtc, RTC_CCR);
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return 0;
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}
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static const struct rtc_class_ops armada38x_rtc_ops = {
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.read_time = armada38x_rtc_read_time,
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.set_time = armada38x_rtc_set_time,
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.read_alarm = armada38x_rtc_read_alarm,
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.set_alarm = armada38x_rtc_set_alarm,
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.alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
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.read_offset = armada38x_rtc_read_offset,
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.set_offset = armada38x_rtc_set_offset,
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};
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static const struct armada38x_rtc_data armada38x_data = {
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.update_mbus_timing = rtc_update_38x_mbus_timing_params,
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.read_rtc_reg = read_rtc_register_38x_wa,
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.clear_isr = armada38x_clear_isr,
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.unmask_interrupt = armada38x_unmask_interrupt,
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.alarm = ALARM1,
|
|
};
|
|
|
|
static const struct armada38x_rtc_data armada8k_data = {
|
|
.update_mbus_timing = rtc_update_8k_mbus_timing_params,
|
|
.read_rtc_reg = read_rtc_register,
|
|
.clear_isr = armada8k_clear_isr,
|
|
.unmask_interrupt = armada8k_unmask_interrupt,
|
|
.alarm = ALARM2,
|
|
};
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id armada38x_rtc_of_match_table[] = {
|
|
{
|
|
.compatible = "marvell,armada-380-rtc",
|
|
.data = &armada38x_data,
|
|
},
|
|
{
|
|
.compatible = "marvell,armada-8k-rtc",
|
|
.data = &armada8k_data,
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
|
|
#endif
|
|
|
|
static __init int armada38x_rtc_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
struct armada38x_rtc *rtc;
|
|
|
|
rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
|
|
GFP_KERNEL);
|
|
if (!rtc)
|
|
return -ENOMEM;
|
|
|
|
rtc->data = of_device_get_match_data(&pdev->dev);
|
|
|
|
rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR,
|
|
sizeof(struct value_to_freq), GFP_KERNEL);
|
|
if (!rtc->val_to_freq)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&rtc->lock);
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
|
|
rtc->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(rtc->regs))
|
|
return PTR_ERR(rtc->regs);
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
|
|
rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(rtc->regs_soc))
|
|
return PTR_ERR(rtc->regs_soc);
|
|
|
|
rtc->irq = platform_get_irq(pdev, 0);
|
|
if (rtc->irq < 0)
|
|
return rtc->irq;
|
|
|
|
rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
|
|
if (IS_ERR(rtc->rtc_dev))
|
|
return PTR_ERR(rtc->rtc_dev);
|
|
|
|
if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
|
|
0, pdev->name, rtc) < 0) {
|
|
dev_warn(&pdev->dev, "Interrupt not available.\n");
|
|
rtc->irq = -1;
|
|
}
|
|
platform_set_drvdata(pdev, rtc);
|
|
|
|
if (rtc->irq != -1)
|
|
device_init_wakeup(&pdev->dev, 1);
|
|
else
|
|
clear_bit(RTC_FEATURE_ALARM, rtc->rtc_dev->features);
|
|
|
|
/* Update RTC-MBUS bridge timing parameters */
|
|
rtc->data->update_mbus_timing(rtc);
|
|
|
|
rtc->rtc_dev->ops = &armada38x_rtc_ops;
|
|
rtc->rtc_dev->range_max = U32_MAX;
|
|
|
|
return devm_rtc_register_device(rtc->rtc_dev);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int armada38x_rtc_suspend(struct device *dev)
|
|
{
|
|
if (device_may_wakeup(dev)) {
|
|
struct armada38x_rtc *rtc = dev_get_drvdata(dev);
|
|
|
|
return enable_irq_wake(rtc->irq);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int armada38x_rtc_resume(struct device *dev)
|
|
{
|
|
if (device_may_wakeup(dev)) {
|
|
struct armada38x_rtc *rtc = dev_get_drvdata(dev);
|
|
|
|
/* Update RTC-MBUS bridge timing parameters */
|
|
rtc->data->update_mbus_timing(rtc);
|
|
|
|
return disable_irq_wake(rtc->irq);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
|
|
armada38x_rtc_suspend, armada38x_rtc_resume);
|
|
|
|
static struct platform_driver armada38x_rtc_driver = {
|
|
.driver = {
|
|
.name = "armada38x-rtc",
|
|
.pm = &armada38x_rtc_pm_ops,
|
|
.of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
|
|
},
|
|
};
|
|
|
|
module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);
|
|
|
|
MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
|
|
MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
|
|
MODULE_LICENSE("GPL");
|