327 lines
8.1 KiB
C
327 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Motorola CPCAP PMIC RTC driver
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*
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* Based on cpcap-regulator.c from Motorola Linux kernel tree
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* Copyright (C) 2009 Motorola, Inc.
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*
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* Rewritten for mainline kernel
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* - use DT
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* - use regmap
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* - use standard interrupt framework
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* - use managed device resources
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* - remove custom "secure clock daemon" helpers
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*
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* Copyright (C) 2017 Sebastian Reichel <sre@kernel.org>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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#include <linux/err.h>
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#include <linux/regmap.h>
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#include <linux/mfd/motorola-cpcap.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#define SECS_PER_DAY 86400
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#define DAY_MASK 0x7FFF
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#define TOD1_MASK 0x00FF
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#define TOD2_MASK 0x01FF
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struct cpcap_time {
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int day;
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int tod1;
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int tod2;
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};
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struct cpcap_rtc {
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struct regmap *regmap;
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struct rtc_device *rtc_dev;
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u16 vendor;
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int alarm_irq;
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bool alarm_enabled;
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int update_irq;
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bool update_enabled;
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};
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static void cpcap2rtc_time(struct rtc_time *rtc, struct cpcap_time *cpcap)
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{
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unsigned long int tod;
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unsigned long int time;
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tod = (cpcap->tod1 & TOD1_MASK) | ((cpcap->tod2 & TOD2_MASK) << 8);
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time = tod + ((cpcap->day & DAY_MASK) * SECS_PER_DAY);
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rtc_time64_to_tm(time, rtc);
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}
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static void rtc2cpcap_time(struct cpcap_time *cpcap, struct rtc_time *rtc)
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{
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unsigned long time;
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time = rtc_tm_to_time64(rtc);
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cpcap->day = time / SECS_PER_DAY;
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time %= SECS_PER_DAY;
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cpcap->tod2 = (time >> 8) & TOD2_MASK;
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cpcap->tod1 = time & TOD1_MASK;
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}
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static int cpcap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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struct cpcap_rtc *rtc = dev_get_drvdata(dev);
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if (rtc->alarm_enabled == enabled)
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return 0;
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if (enabled)
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enable_irq(rtc->alarm_irq);
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else
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disable_irq(rtc->alarm_irq);
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rtc->alarm_enabled = !!enabled;
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return 0;
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}
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static int cpcap_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct cpcap_rtc *rtc;
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struct cpcap_time cpcap_tm;
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int temp_tod2;
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int ret;
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rtc = dev_get_drvdata(dev);
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ret = regmap_read(rtc->regmap, CPCAP_REG_TOD2, &temp_tod2);
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ret |= regmap_read(rtc->regmap, CPCAP_REG_DAY, &cpcap_tm.day);
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ret |= regmap_read(rtc->regmap, CPCAP_REG_TOD1, &cpcap_tm.tod1);
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ret |= regmap_read(rtc->regmap, CPCAP_REG_TOD2, &cpcap_tm.tod2);
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if (temp_tod2 > cpcap_tm.tod2)
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ret |= regmap_read(rtc->regmap, CPCAP_REG_DAY, &cpcap_tm.day);
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if (ret) {
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dev_err(dev, "Failed to read time\n");
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return -EIO;
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}
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cpcap2rtc_time(tm, &cpcap_tm);
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return 0;
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}
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static int cpcap_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct cpcap_rtc *rtc;
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struct cpcap_time cpcap_tm;
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int ret = 0;
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rtc = dev_get_drvdata(dev);
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rtc2cpcap_time(&cpcap_tm, tm);
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if (rtc->alarm_enabled)
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disable_irq(rtc->alarm_irq);
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if (rtc->update_enabled)
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disable_irq(rtc->update_irq);
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if (rtc->vendor == CPCAP_VENDOR_ST) {
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/* The TOD1 and TOD2 registers MUST be written in this order
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* for the change to properly set.
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*/
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ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD1,
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TOD1_MASK, cpcap_tm.tod1);
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ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD2,
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TOD2_MASK, cpcap_tm.tod2);
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ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_DAY,
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DAY_MASK, cpcap_tm.day);
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} else {
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/* Clearing the upper lower 8 bits of the TOD guarantees that
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* the upper half of TOD (TOD2) will not increment for 0xFF RTC
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* ticks (255 seconds). During this time we can safely write
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* to DAY, TOD2, then TOD1 (in that order) and expect RTC to be
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* synchronized to the exact time requested upon the final write
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* to TOD1.
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*/
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ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD1,
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TOD1_MASK, 0);
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ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_DAY,
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DAY_MASK, cpcap_tm.day);
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ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD2,
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TOD2_MASK, cpcap_tm.tod2);
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ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD1,
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TOD1_MASK, cpcap_tm.tod1);
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}
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if (rtc->update_enabled)
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enable_irq(rtc->update_irq);
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if (rtc->alarm_enabled)
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enable_irq(rtc->alarm_irq);
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return ret;
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}
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static int cpcap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct cpcap_rtc *rtc;
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struct cpcap_time cpcap_tm;
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int ret;
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rtc = dev_get_drvdata(dev);
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alrm->enabled = rtc->alarm_enabled;
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ret = regmap_read(rtc->regmap, CPCAP_REG_DAYA, &cpcap_tm.day);
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ret |= regmap_read(rtc->regmap, CPCAP_REG_TODA2, &cpcap_tm.tod2);
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ret |= regmap_read(rtc->regmap, CPCAP_REG_TODA1, &cpcap_tm.tod1);
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if (ret) {
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dev_err(dev, "Failed to read time\n");
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return -EIO;
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}
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cpcap2rtc_time(&alrm->time, &cpcap_tm);
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return rtc_valid_tm(&alrm->time);
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}
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static int cpcap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct cpcap_rtc *rtc;
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struct cpcap_time cpcap_tm;
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int ret;
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rtc = dev_get_drvdata(dev);
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rtc2cpcap_time(&cpcap_tm, &alrm->time);
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if (rtc->alarm_enabled)
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disable_irq(rtc->alarm_irq);
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ret = regmap_update_bits(rtc->regmap, CPCAP_REG_DAYA, DAY_MASK,
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cpcap_tm.day);
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ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TODA2, TOD2_MASK,
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cpcap_tm.tod2);
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ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TODA1, TOD1_MASK,
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cpcap_tm.tod1);
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if (!ret) {
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enable_irq(rtc->alarm_irq);
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rtc->alarm_enabled = true;
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}
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return ret;
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}
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static const struct rtc_class_ops cpcap_rtc_ops = {
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.read_time = cpcap_rtc_read_time,
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.set_time = cpcap_rtc_set_time,
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.read_alarm = cpcap_rtc_read_alarm,
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.set_alarm = cpcap_rtc_set_alarm,
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.alarm_irq_enable = cpcap_rtc_alarm_irq_enable,
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};
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static irqreturn_t cpcap_rtc_alarm_irq(int irq, void *data)
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{
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struct cpcap_rtc *rtc = data;
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rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
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return IRQ_HANDLED;
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}
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static irqreturn_t cpcap_rtc_update_irq(int irq, void *data)
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{
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struct cpcap_rtc *rtc = data;
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rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
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return IRQ_HANDLED;
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}
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static int cpcap_rtc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct cpcap_rtc *rtc;
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int err;
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rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
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if (!rtc)
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return -ENOMEM;
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rtc->regmap = dev_get_regmap(dev->parent, NULL);
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if (!rtc->regmap)
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return -ENODEV;
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platform_set_drvdata(pdev, rtc);
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rtc->rtc_dev = devm_rtc_allocate_device(dev);
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if (IS_ERR(rtc->rtc_dev))
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return PTR_ERR(rtc->rtc_dev);
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rtc->rtc_dev->ops = &cpcap_rtc_ops;
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rtc->rtc_dev->range_max = (timeu64_t) (DAY_MASK + 1) * SECS_PER_DAY - 1;
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err = cpcap_get_vendor(dev, rtc->regmap, &rtc->vendor);
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if (err)
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return err;
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rtc->alarm_irq = platform_get_irq(pdev, 0);
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err = devm_request_threaded_irq(dev, rtc->alarm_irq, NULL,
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cpcap_rtc_alarm_irq,
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IRQF_TRIGGER_NONE | IRQF_ONESHOT,
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"rtc_alarm", rtc);
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if (err) {
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dev_err(dev, "Could not request alarm irq: %d\n", err);
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return err;
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}
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disable_irq(rtc->alarm_irq);
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/* Stock Android uses the 1 Hz interrupt for "secure clock daemon",
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* which is not supported by the mainline kernel. The mainline kernel
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* does not use the irq at the moment, but we explicitly request and
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* disable it, so that its masked and does not wake up the processor
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* every second.
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*/
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rtc->update_irq = platform_get_irq(pdev, 1);
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err = devm_request_threaded_irq(dev, rtc->update_irq, NULL,
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cpcap_rtc_update_irq,
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IRQF_TRIGGER_NONE | IRQF_ONESHOT,
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"rtc_1hz", rtc);
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if (err) {
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dev_err(dev, "Could not request update irq: %d\n", err);
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return err;
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}
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disable_irq(rtc->update_irq);
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err = device_init_wakeup(dev, 1);
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if (err) {
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dev_err(dev, "wakeup initialization failed (%d)\n", err);
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/* ignore error and continue without wakeup support */
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}
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return devm_rtc_register_device(rtc->rtc_dev);
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}
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static const struct of_device_id cpcap_rtc_of_match[] = {
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{ .compatible = "motorola,cpcap-rtc", },
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{},
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};
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MODULE_DEVICE_TABLE(of, cpcap_rtc_of_match);
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static struct platform_driver cpcap_rtc_driver = {
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.probe = cpcap_rtc_probe,
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.driver = {
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.name = "cpcap-rtc",
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.of_match_table = cpcap_rtc_of_match,
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},
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};
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module_platform_driver(cpcap_rtc_driver);
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MODULE_ALIAS("platform:cpcap-rtc");
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MODULE_DESCRIPTION("CPCAP RTC driver");
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MODULE_AUTHOR("Sebastian Reichel <sre@kernel.org>");
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MODULE_LICENSE("GPL");
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