361 lines
8.6 KiB
C
361 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2010 NXP Semiconductors
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/rtc.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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/*
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* Clock and Power control register offsets
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*/
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#define LPC32XX_RTC_UCOUNT 0x00
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#define LPC32XX_RTC_DCOUNT 0x04
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#define LPC32XX_RTC_MATCH0 0x08
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#define LPC32XX_RTC_MATCH1 0x0C
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#define LPC32XX_RTC_CTRL 0x10
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#define LPC32XX_RTC_INTSTAT 0x14
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#define LPC32XX_RTC_KEY 0x18
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#define LPC32XX_RTC_SRAM 0x80
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#define LPC32XX_RTC_CTRL_MATCH0 (1 << 0)
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#define LPC32XX_RTC_CTRL_MATCH1 (1 << 1)
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#define LPC32XX_RTC_CTRL_ONSW_MATCH0 (1 << 2)
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#define LPC32XX_RTC_CTRL_ONSW_MATCH1 (1 << 3)
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#define LPC32XX_RTC_CTRL_SW_RESET (1 << 4)
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#define LPC32XX_RTC_CTRL_CNTR_DIS (1 << 6)
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#define LPC32XX_RTC_CTRL_ONSW_FORCE_HI (1 << 7)
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#define LPC32XX_RTC_INTSTAT_MATCH0 (1 << 0)
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#define LPC32XX_RTC_INTSTAT_MATCH1 (1 << 1)
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#define LPC32XX_RTC_INTSTAT_ONSW (1 << 2)
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#define LPC32XX_RTC_KEY_ONSW_LOADVAL 0xB5C13F27
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#define rtc_readl(dev, reg) \
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__raw_readl((dev)->rtc_base + (reg))
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#define rtc_writel(dev, reg, val) \
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__raw_writel((val), (dev)->rtc_base + (reg))
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struct lpc32xx_rtc {
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void __iomem *rtc_base;
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int irq;
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unsigned char alarm_enabled;
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struct rtc_device *rtc;
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spinlock_t lock;
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};
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static int lpc32xx_rtc_read_time(struct device *dev, struct rtc_time *time)
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{
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unsigned long elapsed_sec;
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struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
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elapsed_sec = rtc_readl(rtc, LPC32XX_RTC_UCOUNT);
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rtc_time64_to_tm(elapsed_sec, time);
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return 0;
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}
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static int lpc32xx_rtc_set_time(struct device *dev, struct rtc_time *time)
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{
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struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
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u32 secs = rtc_tm_to_time64(time);
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u32 tmp;
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spin_lock_irq(&rtc->lock);
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/* RTC must be disabled during count update */
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tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
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rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp | LPC32XX_RTC_CTRL_CNTR_DIS);
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rtc_writel(rtc, LPC32XX_RTC_UCOUNT, secs);
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rtc_writel(rtc, LPC32XX_RTC_DCOUNT, 0xFFFFFFFF - secs);
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rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp &= ~LPC32XX_RTC_CTRL_CNTR_DIS);
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spin_unlock_irq(&rtc->lock);
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return 0;
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}
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static int lpc32xx_rtc_read_alarm(struct device *dev,
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struct rtc_wkalrm *wkalrm)
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{
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struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
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rtc_time64_to_tm(rtc_readl(rtc, LPC32XX_RTC_MATCH0), &wkalrm->time);
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wkalrm->enabled = rtc->alarm_enabled;
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wkalrm->pending = !!(rtc_readl(rtc, LPC32XX_RTC_INTSTAT) &
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LPC32XX_RTC_INTSTAT_MATCH0);
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return rtc_valid_tm(&wkalrm->time);
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}
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static int lpc32xx_rtc_set_alarm(struct device *dev,
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struct rtc_wkalrm *wkalrm)
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{
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struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
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unsigned long alarmsecs;
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u32 tmp;
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alarmsecs = rtc_tm_to_time64(&wkalrm->time);
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spin_lock_irq(&rtc->lock);
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/* Disable alarm during update */
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tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
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rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp & ~LPC32XX_RTC_CTRL_MATCH0);
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rtc_writel(rtc, LPC32XX_RTC_MATCH0, alarmsecs);
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rtc->alarm_enabled = wkalrm->enabled;
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if (wkalrm->enabled) {
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rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
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LPC32XX_RTC_INTSTAT_MATCH0);
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rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp |
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LPC32XX_RTC_CTRL_MATCH0);
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}
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spin_unlock_irq(&rtc->lock);
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return 0;
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}
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static int lpc32xx_rtc_alarm_irq_enable(struct device *dev,
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unsigned int enabled)
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{
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struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
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u32 tmp;
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spin_lock_irq(&rtc->lock);
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tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
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if (enabled) {
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rtc->alarm_enabled = 1;
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tmp |= LPC32XX_RTC_CTRL_MATCH0;
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} else {
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rtc->alarm_enabled = 0;
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tmp &= ~LPC32XX_RTC_CTRL_MATCH0;
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}
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rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
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spin_unlock_irq(&rtc->lock);
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return 0;
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}
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static irqreturn_t lpc32xx_rtc_alarm_interrupt(int irq, void *dev)
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{
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struct lpc32xx_rtc *rtc = dev;
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spin_lock(&rtc->lock);
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/* Disable alarm interrupt */
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rtc_writel(rtc, LPC32XX_RTC_CTRL,
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rtc_readl(rtc, LPC32XX_RTC_CTRL) &
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~LPC32XX_RTC_CTRL_MATCH0);
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rtc->alarm_enabled = 0;
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/*
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* Write a large value to the match value so the RTC won't
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* keep firing the match status
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*/
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rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
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rtc_writel(rtc, LPC32XX_RTC_INTSTAT, LPC32XX_RTC_INTSTAT_MATCH0);
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spin_unlock(&rtc->lock);
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rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
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return IRQ_HANDLED;
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}
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static const struct rtc_class_ops lpc32xx_rtc_ops = {
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.read_time = lpc32xx_rtc_read_time,
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.set_time = lpc32xx_rtc_set_time,
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.read_alarm = lpc32xx_rtc_read_alarm,
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.set_alarm = lpc32xx_rtc_set_alarm,
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.alarm_irq_enable = lpc32xx_rtc_alarm_irq_enable,
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};
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static int lpc32xx_rtc_probe(struct platform_device *pdev)
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{
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struct lpc32xx_rtc *rtc;
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int err;
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u32 tmp;
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rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
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if (unlikely(!rtc))
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return -ENOMEM;
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rtc->rtc_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(rtc->rtc_base))
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return PTR_ERR(rtc->rtc_base);
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spin_lock_init(&rtc->lock);
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/*
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* The RTC is on a separate power domain and can keep it's state
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* across a chip power cycle. If the RTC has never been previously
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* setup, then set it up now for the first time.
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*/
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tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
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if (rtc_readl(rtc, LPC32XX_RTC_KEY) != LPC32XX_RTC_KEY_ONSW_LOADVAL) {
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tmp &= ~(LPC32XX_RTC_CTRL_SW_RESET |
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LPC32XX_RTC_CTRL_CNTR_DIS |
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LPC32XX_RTC_CTRL_MATCH0 |
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LPC32XX_RTC_CTRL_MATCH1 |
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LPC32XX_RTC_CTRL_ONSW_MATCH0 |
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LPC32XX_RTC_CTRL_ONSW_MATCH1 |
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LPC32XX_RTC_CTRL_ONSW_FORCE_HI);
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rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
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/* Clear latched interrupt states */
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rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
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rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
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LPC32XX_RTC_INTSTAT_MATCH0 |
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LPC32XX_RTC_INTSTAT_MATCH1 |
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LPC32XX_RTC_INTSTAT_ONSW);
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/* Write key value to RTC so it won't reload on reset */
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rtc_writel(rtc, LPC32XX_RTC_KEY,
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LPC32XX_RTC_KEY_ONSW_LOADVAL);
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} else {
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rtc_writel(rtc, LPC32XX_RTC_CTRL,
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tmp & ~LPC32XX_RTC_CTRL_MATCH0);
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}
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platform_set_drvdata(pdev, rtc);
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rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
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if (IS_ERR(rtc->rtc))
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return PTR_ERR(rtc->rtc);
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rtc->rtc->ops = &lpc32xx_rtc_ops;
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rtc->rtc->range_max = U32_MAX;
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err = devm_rtc_register_device(rtc->rtc);
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if (err)
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return err;
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/*
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* IRQ is enabled after device registration in case alarm IRQ
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* is pending upon suspend exit.
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*/
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rtc->irq = platform_get_irq(pdev, 0);
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if (rtc->irq < 0) {
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dev_warn(&pdev->dev, "Can't get interrupt resource\n");
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} else {
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if (devm_request_irq(&pdev->dev, rtc->irq,
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lpc32xx_rtc_alarm_interrupt,
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0, pdev->name, rtc) < 0) {
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dev_warn(&pdev->dev, "Can't request interrupt.\n");
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rtc->irq = -1;
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} else {
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device_init_wakeup(&pdev->dev, 1);
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}
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}
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return 0;
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}
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#ifdef CONFIG_PM
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static int lpc32xx_rtc_suspend(struct device *dev)
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{
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struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
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if (rtc->irq >= 0) {
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if (device_may_wakeup(dev))
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enable_irq_wake(rtc->irq);
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else
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disable_irq_wake(rtc->irq);
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}
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return 0;
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}
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static int lpc32xx_rtc_resume(struct device *dev)
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{
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struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
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if (rtc->irq >= 0 && device_may_wakeup(dev))
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disable_irq_wake(rtc->irq);
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return 0;
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}
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/* Unconditionally disable the alarm */
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static int lpc32xx_rtc_freeze(struct device *dev)
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{
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struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
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spin_lock_irq(&rtc->lock);
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rtc_writel(rtc, LPC32XX_RTC_CTRL,
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rtc_readl(rtc, LPC32XX_RTC_CTRL) &
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~LPC32XX_RTC_CTRL_MATCH0);
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spin_unlock_irq(&rtc->lock);
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return 0;
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}
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static int lpc32xx_rtc_thaw(struct device *dev)
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{
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struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
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if (rtc->alarm_enabled) {
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spin_lock_irq(&rtc->lock);
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rtc_writel(rtc, LPC32XX_RTC_CTRL,
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rtc_readl(rtc, LPC32XX_RTC_CTRL) |
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LPC32XX_RTC_CTRL_MATCH0);
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spin_unlock_irq(&rtc->lock);
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}
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return 0;
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}
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static const struct dev_pm_ops lpc32xx_rtc_pm_ops = {
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.suspend = lpc32xx_rtc_suspend,
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.resume = lpc32xx_rtc_resume,
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.freeze = lpc32xx_rtc_freeze,
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.thaw = lpc32xx_rtc_thaw,
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.restore = lpc32xx_rtc_resume
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};
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#define LPC32XX_RTC_PM_OPS (&lpc32xx_rtc_pm_ops)
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#else
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#define LPC32XX_RTC_PM_OPS NULL
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#endif
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#ifdef CONFIG_OF
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static const struct of_device_id lpc32xx_rtc_match[] = {
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{ .compatible = "nxp,lpc3220-rtc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, lpc32xx_rtc_match);
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#endif
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static struct platform_driver lpc32xx_rtc_driver = {
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.probe = lpc32xx_rtc_probe,
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.driver = {
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.name = "rtc-lpc32xx",
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.pm = LPC32XX_RTC_PM_OPS,
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.of_match_table = of_match_ptr(lpc32xx_rtc_match),
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},
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};
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module_platform_driver(lpc32xx_rtc_driver);
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MODULE_AUTHOR("Kevin Wells <wellsk40@gmail.com");
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MODULE_DESCRIPTION("RTC driver for the LPC32xx SoC");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:rtc-lpc32xx");
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