344 lines
9.0 KiB
C
344 lines
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Qualcomm Ramp Controller driver
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* Copyright (c) 2022, AngeloGioacchino Del Regno
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* <angelogioacchino.delregno@collabora.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#define RC_UPDATE_EN BIT(0)
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#define RC_ROOT_EN BIT(1)
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#define RC_REG_CFG_UPDATE 0x60
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#define RC_CFG_UPDATE_EN BIT(8)
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#define RC_CFG_ACK GENMASK(31, 16)
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#define RC_DCVS_CFG_SID 2
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#define RC_LINK_SID 3
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#define RC_LMH_SID 6
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#define RC_DFS_SID 14
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#define RC_UPDATE_TIMEOUT_US 500
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/**
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* struct qcom_ramp_controller_desc - SoC specific parameters
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* @cfg_dfs_sid: Dynamic Frequency Scaling SID configuration
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* @cfg_link_sid: Link SID configuration
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* @cfg_lmh_sid: Limits Management hardware SID configuration
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* @cfg_ramp_en: Ramp Controller enable sequence
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* @cfg_ramp_dis: Ramp Controller disable sequence
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* @cmd_reg: Command register offset
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* @num_dfs_sids: Number of DFS SIDs (max 8)
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* @num_link_sids: Number of Link SIDs (max 3)
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* @num_lmh_sids: Number of LMh SIDs (max 8)
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* @num_ramp_en: Number of entries in enable sequence
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* @num_ramp_dis: Number of entries in disable sequence
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*/
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struct qcom_ramp_controller_desc {
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const struct reg_sequence *cfg_dfs_sid;
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const struct reg_sequence *cfg_link_sid;
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const struct reg_sequence *cfg_lmh_sid;
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const struct reg_sequence *cfg_ramp_en;
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const struct reg_sequence *cfg_ramp_dis;
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u8 cmd_reg;
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u8 num_dfs_sids;
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u8 num_link_sids;
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u8 num_lmh_sids;
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u8 num_ramp_en;
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u8 num_ramp_dis;
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};
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/**
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* struct qcom_ramp_controller - Main driver structure
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* @regmap: Regmap handle
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* @desc: SoC specific parameters
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*/
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struct qcom_ramp_controller {
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struct regmap *regmap;
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const struct qcom_ramp_controller_desc *desc;
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};
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/**
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* rc_wait_for_update() - Wait for Ramp Controller root update
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* @qrc: Main driver structure
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*
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* Return: Zero for success or negative number for failure
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*/
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static int rc_wait_for_update(struct qcom_ramp_controller *qrc)
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{
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const struct qcom_ramp_controller_desc *d = qrc->desc;
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struct regmap *r = qrc->regmap;
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u32 val;
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int ret;
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ret = regmap_set_bits(r, d->cmd_reg, RC_ROOT_EN);
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if (ret)
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return ret;
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return regmap_read_poll_timeout(r, d->cmd_reg, val, !(val & RC_UPDATE_EN),
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1, RC_UPDATE_TIMEOUT_US);
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}
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/**
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* rc_set_cfg_update() - Ramp Controller configuration update
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* @qrc: Main driver structure
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* @ce: Configuration entry to update
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*
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* Return: Zero for success or negative number for failure
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*/
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static int rc_set_cfg_update(struct qcom_ramp_controller *qrc, u8 ce)
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{
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const struct qcom_ramp_controller_desc *d = qrc->desc;
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struct regmap *r = qrc->regmap;
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u32 ack, val;
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int ret;
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/* The ack bit is between bits 16-31 of RC_REG_CFG_UPDATE */
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ack = FIELD_PREP(RC_CFG_ACK, BIT(ce));
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/* Write the configuration type first... */
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ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, ce);
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if (ret)
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return ret;
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/* ...and after that, enable the update bit to sync the changes */
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ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, RC_CFG_UPDATE_EN);
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if (ret)
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return ret;
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/* Wait for the changes to go through */
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ret = regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE, val,
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val & ack, 1, RC_UPDATE_TIMEOUT_US);
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if (ret)
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return ret;
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/*
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* Configuration update success! The CFG_UPDATE register will not be
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* cleared automatically upon applying the configuration, so we have
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* to do that manually in order to leave the ramp controller in a
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* predictable and clean state.
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*/
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ret = regmap_write(r, d->cmd_reg + RC_REG_CFG_UPDATE, 0);
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if (ret)
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return ret;
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/* Wait for the update bit cleared ack */
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return regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE,
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val, !(val & RC_CFG_ACK), 1,
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RC_UPDATE_TIMEOUT_US);
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}
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/**
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* rc_write_cfg - Send configuration sequence
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* @qrc: Main driver structure
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* @seq: Register sequence to send before asking for update
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* @ce: Configuration SID
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* @nsids: Total number of SIDs
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*
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* Returns: Zero for success or negative number for error
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*/
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static int rc_write_cfg(struct qcom_ramp_controller *qrc,
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const struct reg_sequence *seq,
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u16 ce, u8 nsids)
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{
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int ret;
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u8 i;
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/* Check if, and wait until the ramp controller is ready */
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ret = rc_wait_for_update(qrc);
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if (ret)
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return ret;
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/* Write the sequence */
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ret = regmap_multi_reg_write(qrc->regmap, seq, nsids);
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if (ret)
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return ret;
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/* Pull the trigger: do config update starting from the last sid */
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for (i = 0; i < nsids; i++) {
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ret = rc_set_cfg_update(qrc, (u8)ce - i);
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if (ret)
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return ret;
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}
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return 0;
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}
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/**
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* rc_ramp_ctrl_enable() - Enable Ramp up/down Control
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* @qrc: Main driver structure
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*
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* Return: Zero for success or negative number for error
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*/
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static int rc_ramp_ctrl_enable(struct qcom_ramp_controller *qrc)
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{
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const struct qcom_ramp_controller_desc *d = qrc->desc;
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int i, ret;
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for (i = 0; i < d->num_ramp_en; i++) {
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ret = rc_write_cfg(qrc, &d->cfg_ramp_en[i], RC_DCVS_CFG_SID, 1);
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if (ret)
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return ret;
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}
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return 0;
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}
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/**
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* qcom_ramp_controller_start() - Initialize and start the ramp controller
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* @qrc: Main driver structure
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*
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* The Ramp Controller needs to be initialized by programming the relevant
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* registers with SoC-specific configuration: once programming is done,
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* the hardware will take care of the rest (no further handling required).
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*
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* Return: Zero for success or negative number for error
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*/
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static int qcom_ramp_controller_start(struct qcom_ramp_controller *qrc)
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{
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const struct qcom_ramp_controller_desc *d = qrc->desc;
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int ret;
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/* Program LMH, DFS, Link SIDs */
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ret = rc_write_cfg(qrc, d->cfg_lmh_sid, RC_LMH_SID, d->num_lmh_sids);
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if (ret)
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return ret;
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ret = rc_write_cfg(qrc, d->cfg_dfs_sid, RC_DFS_SID, d->num_dfs_sids);
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if (ret)
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return ret;
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ret = rc_write_cfg(qrc, d->cfg_link_sid, RC_LINK_SID, d->num_link_sids);
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if (ret)
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return ret;
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/* Everything is ready! Enable the ramp up/down control */
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return rc_ramp_ctrl_enable(qrc);
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}
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static const struct regmap_config qrc_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x68,
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.fast_io = true,
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};
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static const struct reg_sequence msm8976_cfg_dfs_sid[] = {
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{ 0x10, 0xfefebff7 },
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{ 0x14, 0xfdff7fef },
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{ 0x18, 0xfbffdefb },
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{ 0x1c, 0xb69b5555 },
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{ 0x20, 0x24929249 },
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{ 0x24, 0x49241112 },
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{ 0x28, 0x11112111 },
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{ 0x2c, 0x8102 }
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};
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static const struct reg_sequence msm8976_cfg_link_sid[] = {
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{ 0x40, 0xfc987 }
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};
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static const struct reg_sequence msm8976_cfg_lmh_sid[] = {
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{ 0x30, 0x77706db },
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{ 0x34, 0x5550249 },
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{ 0x38, 0x111 }
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};
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static const struct reg_sequence msm8976_cfg_ramp_en[] = {
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{ 0x50, 0x800 }, /* pre_en */
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{ 0x50, 0xc00 }, /* en */
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{ 0x50, 0x400 } /* post_en */
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};
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static const struct reg_sequence msm8976_cfg_ramp_dis[] = {
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{ 0x50, 0x0 }
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};
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static const struct qcom_ramp_controller_desc msm8976_rc_cfg = {
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.cfg_dfs_sid = msm8976_cfg_dfs_sid,
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.num_dfs_sids = ARRAY_SIZE(msm8976_cfg_dfs_sid),
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.cfg_link_sid = msm8976_cfg_link_sid,
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.num_link_sids = ARRAY_SIZE(msm8976_cfg_link_sid),
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.cfg_lmh_sid = msm8976_cfg_lmh_sid,
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.num_lmh_sids = ARRAY_SIZE(msm8976_cfg_lmh_sid),
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.cfg_ramp_en = msm8976_cfg_ramp_en,
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.num_ramp_en = ARRAY_SIZE(msm8976_cfg_ramp_en),
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.cfg_ramp_dis = msm8976_cfg_ramp_dis,
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.num_ramp_dis = ARRAY_SIZE(msm8976_cfg_ramp_dis),
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.cmd_reg = 0x0,
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};
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static int qcom_ramp_controller_probe(struct platform_device *pdev)
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{
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struct qcom_ramp_controller *qrc;
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void __iomem *base;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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qrc = devm_kmalloc(&pdev->dev, sizeof(*qrc), GFP_KERNEL);
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if (!qrc)
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return -ENOMEM;
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qrc->desc = device_get_match_data(&pdev->dev);
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if (!qrc->desc)
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return -EINVAL;
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qrc->regmap = devm_regmap_init_mmio(&pdev->dev, base, &qrc_regmap_config);
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if (IS_ERR(qrc->regmap))
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return PTR_ERR(qrc->regmap);
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platform_set_drvdata(pdev, qrc);
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return qcom_ramp_controller_start(qrc);
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}
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static int qcom_ramp_controller_remove(struct platform_device *pdev)
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{
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struct qcom_ramp_controller *qrc = platform_get_drvdata(pdev);
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return rc_write_cfg(qrc, qrc->desc->cfg_ramp_dis,
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RC_DCVS_CFG_SID, qrc->desc->num_ramp_dis);
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}
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static const struct of_device_id qcom_ramp_controller_match_table[] = {
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{ .compatible = "qcom,msm8976-ramp-controller", .data = &msm8976_rc_cfg },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, qcom_ramp_controller_match_table);
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static struct platform_driver qcom_ramp_controller_driver = {
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.driver = {
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.name = "qcom-ramp-controller",
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.of_match_table = qcom_ramp_controller_match_table,
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.suppress_bind_attrs = true,
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},
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.probe = qcom_ramp_controller_probe,
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.remove = qcom_ramp_controller_remove,
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};
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static int __init qcom_ramp_controller_init(void)
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{
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return platform_driver_register(&qcom_ramp_controller_driver);
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}
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arch_initcall(qcom_ramp_controller_init);
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MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
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MODULE_DESCRIPTION("Qualcomm Ramp Controller driver");
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MODULE_LICENSE("GPL");
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