81 lines
2.0 KiB
C
81 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/arm-smccc.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/panic_notifier.h>
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#define SMC_SIP_INVOKE_MCE 0xc2ffff00
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#define MCE_SMC_READ_MCA 12
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#define MCA_ARI_CMD_RD_SERR 1
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#define MCA_ARI_RW_SUBIDX_STAT 1
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#define SERR_STATUS_VAL BIT_ULL(63)
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#define MCA_ARI_RW_SUBIDX_ADDR 2
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#define MCA_ARI_RW_SUBIDX_MSC1 3
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#define MCA_ARI_RW_SUBIDX_MSC2 4
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static const char * const bank_names[] = {
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"SYS:DPMU", "ROC:IOB", "ROC:MCB", "ROC:CCE", "ROC:CQX", "ROC:CTU",
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};
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static void read_uncore_mca(u8 cmd, u8 idx, u8 subidx, u8 inst, u64 *data)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(SMC_SIP_INVOKE_MCE | MCE_SMC_READ_MCA,
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((u64)inst << 24) | ((u64)idx << 16) |
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((u64)subidx << 8) | ((u64)cmd << 0),
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0, 0, 0, 0, 0, 0, &res);
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*data = res.a2;
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}
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static int tegra186_ari_panic_handler(struct notifier_block *nb,
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unsigned long code, void *unused)
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{
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u64 status;
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int i;
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for (i = 0; i < ARRAY_SIZE(bank_names); i++) {
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read_uncore_mca(MCA_ARI_CMD_RD_SERR, i, MCA_ARI_RW_SUBIDX_STAT,
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0, &status);
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if (status & SERR_STATUS_VAL) {
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u64 addr, misc1, misc2;
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read_uncore_mca(MCA_ARI_CMD_RD_SERR, i,
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MCA_ARI_RW_SUBIDX_ADDR, 0, &addr);
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read_uncore_mca(MCA_ARI_CMD_RD_SERR, i,
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MCA_ARI_RW_SUBIDX_MSC1, 0, &misc1);
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read_uncore_mca(MCA_ARI_CMD_RD_SERR, i,
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MCA_ARI_RW_SUBIDX_MSC2, 0, &misc2);
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pr_crit("Machine Check Error in %s\n"
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" status=0x%llx addr=0x%llx\n"
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" msc1=0x%llx msc2=0x%llx\n",
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bank_names[i], status, addr, misc1, misc2);
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}
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}
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return NOTIFY_DONE;
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}
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static struct notifier_block tegra186_ari_panic_nb = {
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.notifier_call = tegra186_ari_panic_handler,
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};
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static int __init tegra186_ari_init(void)
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{
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if (of_machine_is_compatible("nvidia,tegra186"))
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atomic_notifier_chain_register(&panic_notifier_list, &tegra186_ari_panic_nb);
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return 0;
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}
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early_initcall(tegra186_ari_init);
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