319 lines
9.3 KiB
C
319 lines
9.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* xHCI host controller driver for R-Car SoCs
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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*/
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#include <linux/firmware.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/usb/phy.h>
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#include <linux/sys_soc.h>
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#include "xhci.h"
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#include "xhci-plat.h"
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#include "xhci-rzv2m.h"
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#define XHCI_RCAR_FIRMWARE_NAME_V1 "r8a779x_usb3_v1.dlmem"
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#define XHCI_RCAR_FIRMWARE_NAME_V2 "r8a779x_usb3_v2.dlmem"
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#define XHCI_RCAR_FIRMWARE_NAME_V3 "r8a779x_usb3_v3.dlmem"
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/*
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* - The V3 firmware is for almost all R-Car Gen3 (except r8a7795 ES1.x)
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* - The V2 firmware is for r8a7795 ES1.x.
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* - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes
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* performance degradation. So, this driver continues to use the V1 if R-Car
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* Gen2.
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* - The V1 firmware is impossible to use on R-Car Gen3.
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*/
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MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1);
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MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V2);
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MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3);
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/*** Register Offset ***/
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#define RCAR_USB3_AXH_STA 0x104 /* AXI Host Control Status */
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#define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */
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#define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
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#define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
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#define RCAR_USB3_LCLK 0xa44 /* LCLK Select */
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#define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */
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#define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */
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#define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */
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#define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */
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#define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */
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/*** Register Settings ***/
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/* AXI Host Control Status */
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#define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE 0x00010000
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#define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE 0x00000001
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#define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE | \
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RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)
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/* Interrupt Enable */
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#define RCAR_USB3_INT_XHC_ENA 0x00000001
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#define RCAR_USB3_INT_PME_ENA 0x00000002
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#define RCAR_USB3_INT_HSE_ENA 0x00000004
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#define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \
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RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
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/* FW Download Control & Status */
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#define RCAR_USB3_DL_CTRL_ENABLE 0x00000001
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#define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010
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#define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100
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/* LCLK Select */
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#define RCAR_USB3_LCLK_ENA_VAL 0x01030001
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/* USB3.0 Configuration */
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#define RCAR_USB3_CONF1_VAL 0x00030204
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#define RCAR_USB3_CONF2_VAL 0x00030300
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#define RCAR_USB3_CONF3_VAL 0x13802007
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/* USB3.0 Polarity */
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#define RCAR_USB3_RX_POL_VAL BIT(21)
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#define RCAR_USB3_TX_POL_VAL BIT(4)
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/* For soc_device_attribute */
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#define RCAR_XHCI_FIRMWARE_V2 BIT(0) /* FIRMWARE V2 */
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static const struct soc_device_attribute rcar_quirks_match[] = {
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{
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.soc_id = "r8a7795", .revision = "ES1.*",
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.data = (void *)RCAR_XHCI_FIRMWARE_V2,
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},
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{ /* sentinel */ }
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};
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static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
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{
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/* LCLK Select */
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writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
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/* USB3.0 Configuration */
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writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
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writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
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writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
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/* USB3.0 Polarity */
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writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
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writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
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}
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static int xhci_rcar_is_gen2(struct device *dev)
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{
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struct device_node *node = dev->of_node;
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return of_device_is_compatible(node, "renesas,xhci-r8a7790") ||
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of_device_is_compatible(node, "renesas,xhci-r8a7791") ||
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of_device_is_compatible(node, "renesas,xhci-r8a7793") ||
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of_device_is_compatible(node, "renesas,rcar-gen2-xhci");
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}
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static void xhci_rcar_start(struct usb_hcd *hcd)
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{
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u32 temp;
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if (hcd->regs != NULL) {
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/* Interrupt Enable */
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temp = readl(hcd->regs + RCAR_USB3_INT_ENA);
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temp |= RCAR_USB3_INT_ENA_VAL;
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writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
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if (xhci_rcar_is_gen2(hcd->self.controller))
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xhci_rcar_start_gen2(hcd);
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}
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}
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static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
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{
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struct device *dev = hcd->self.controller;
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void __iomem *regs = hcd->regs;
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struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
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const struct firmware *fw;
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int retval, index, j;
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u32 data, val, temp;
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u32 quirks = 0;
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const struct soc_device_attribute *attr;
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const char *firmware_name;
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/*
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* According to the datasheet, "Upon the completion of FW Download,
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* there is no need to write or reload FW".
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*/
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if (readl(regs + RCAR_USB3_DL_CTRL) & RCAR_USB3_DL_CTRL_FW_SUCCESS)
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return 0;
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attr = soc_device_match(rcar_quirks_match);
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if (attr)
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quirks = (uintptr_t)attr->data;
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if (quirks & RCAR_XHCI_FIRMWARE_V2)
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firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2;
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else
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firmware_name = priv->firmware_name;
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/* request R-Car USB3.0 firmware */
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retval = request_firmware(&fw, firmware_name, dev);
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if (retval)
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return retval;
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/* download R-Car USB3.0 firmware */
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temp = readl(regs + RCAR_USB3_DL_CTRL);
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temp |= RCAR_USB3_DL_CTRL_ENABLE;
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writel(temp, regs + RCAR_USB3_DL_CTRL);
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for (index = 0; index < fw->size; index += 4) {
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/* to avoid reading beyond the end of the buffer */
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for (data = 0, j = 3; j >= 0; j--) {
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if ((j + index) < fw->size)
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data |= fw->data[index + j] << (8 * j);
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}
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writel(data, regs + RCAR_USB3_FW_DATA0);
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temp = readl(regs + RCAR_USB3_DL_CTRL);
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temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
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writel(temp, regs + RCAR_USB3_DL_CTRL);
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retval = readl_poll_timeout_atomic(regs + RCAR_USB3_DL_CTRL,
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val, !(val & RCAR_USB3_DL_CTRL_FW_SET_DATA0),
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1, 10000);
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if (retval < 0)
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break;
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}
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temp = readl(regs + RCAR_USB3_DL_CTRL);
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temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
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writel(temp, regs + RCAR_USB3_DL_CTRL);
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retval = readl_poll_timeout_atomic((regs + RCAR_USB3_DL_CTRL),
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val, val & RCAR_USB3_DL_CTRL_FW_SUCCESS, 1, 10000);
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release_firmware(fw);
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return retval;
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}
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static bool xhci_rcar_wait_for_pll_active(struct usb_hcd *hcd)
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{
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int retval;
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u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK;
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retval = readl_poll_timeout_atomic(hcd->regs + RCAR_USB3_AXH_STA,
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val, (val & mask) == mask, 1, 1000);
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return !retval;
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}
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/* This function needs to initialize a "phy" of usb before */
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static int xhci_rcar_init_quirk(struct usb_hcd *hcd)
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{
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/* If hcd->regs is NULL, we don't just call the following function */
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if (!hcd->regs)
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return 0;
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if (!xhci_rcar_wait_for_pll_active(hcd))
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return -ETIMEDOUT;
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return xhci_rcar_download_firmware(hcd);
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}
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static int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
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{
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int ret;
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ret = xhci_rcar_download_firmware(hcd);
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if (!ret)
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xhci_rcar_start(hcd);
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return ret;
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}
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/*
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* On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
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* to 1. However, these SoCs don't support 64-bit address memory
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* pointers. So, this driver clears the AC64 bit of xhci->hcc_params
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* to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
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* xhci_gen_setup() by using the XHCI_NO_64BIT_SUPPORT quirk.
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*
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* And, since the firmware/internal CPU control the USBSTS.STS_HALT
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* and the process speed is down when the roothub port enters U3,
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* long delay for the handshake of STS_HALT is neeed in xhci_suspend()
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* by using the XHCI_SLOW_SUSPEND quirk.
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*/
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#define SET_XHCI_PLAT_PRIV_FOR_RCAR(firmware) \
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.firmware_name = firmware, \
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.quirks = XHCI_NO_64BIT_SUPPORT | XHCI_TRUST_TX_LENGTH | \
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XHCI_SLOW_SUSPEND, \
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.init_quirk = xhci_rcar_init_quirk, \
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.plat_start = xhci_rcar_start, \
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.resume_quirk = xhci_rcar_resume_quirk,
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static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen2 = {
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SET_XHCI_PLAT_PRIV_FOR_RCAR(XHCI_RCAR_FIRMWARE_NAME_V1)
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};
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static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen3 = {
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SET_XHCI_PLAT_PRIV_FOR_RCAR(XHCI_RCAR_FIRMWARE_NAME_V3)
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};
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static const struct xhci_plat_priv xhci_plat_renesas_rzv2m = {
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.quirks = XHCI_NO_64BIT_SUPPORT | XHCI_TRUST_TX_LENGTH |
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XHCI_SLOW_SUSPEND,
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.init_quirk = xhci_rzv2m_init_quirk,
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.plat_start = xhci_rzv2m_start,
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};
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static const struct of_device_id usb_xhci_of_match[] = {
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{
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.compatible = "renesas,xhci-r8a7790",
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.data = &xhci_plat_renesas_rcar_gen2,
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}, {
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.compatible = "renesas,xhci-r8a7791",
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.data = &xhci_plat_renesas_rcar_gen2,
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}, {
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.compatible = "renesas,xhci-r8a7793",
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.data = &xhci_plat_renesas_rcar_gen2,
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}, {
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.compatible = "renesas,xhci-r8a7795",
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.data = &xhci_plat_renesas_rcar_gen3,
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}, {
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.compatible = "renesas,xhci-r8a7796",
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.data = &xhci_plat_renesas_rcar_gen3,
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}, {
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.compatible = "renesas,rcar-gen2-xhci",
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.data = &xhci_plat_renesas_rcar_gen2,
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}, {
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.compatible = "renesas,rcar-gen3-xhci",
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.data = &xhci_plat_renesas_rcar_gen3,
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}, {
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.compatible = "renesas,rzv2m-xhci",
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.data = &xhci_plat_renesas_rzv2m,
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, usb_xhci_of_match);
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static int xhci_renesas_probe(struct platform_device *pdev)
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{
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const struct xhci_plat_priv *priv_match;
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priv_match = of_device_get_match_data(&pdev->dev);
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return xhci_plat_probe(pdev, NULL, priv_match);
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}
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static struct platform_driver usb_xhci_renesas_driver = {
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.probe = xhci_renesas_probe,
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.remove = xhci_plat_remove,
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.shutdown = usb_hcd_platform_shutdown,
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.driver = {
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.name = "xhci-renesas-hcd",
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.pm = &xhci_plat_pm_ops,
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.of_match_table = of_match_ptr(usb_xhci_of_match),
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},
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};
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module_platform_driver(usb_xhci_renesas_driver);
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MODULE_DESCRIPTION("xHCI Platform Host Controller Driver for Renesas R-Car and RZ");
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MODULE_LICENSE("GPL");
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