309 lines
9.0 KiB
C
309 lines
9.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Driver for the NXP ISP1760 chip
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*
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* Copyright 2021 Linaro, Rui Miguel Silva
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* Copyright 2014 Laurent Pinchart
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* Copyright 2007 Sebastian Siewior
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*
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* Contacts:
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* Sebastian Siewior <bigeasy@linutronix.de>
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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* Rui Miguel Silva <rui.silva@linaro.org>
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*/
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#ifndef _ISP176x_REGS_H_
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#define _ISP176x_REGS_H_
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/* -----------------------------------------------------------------------------
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* Host Controller
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*/
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/* ISP1760/31 */
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/* EHCI capability registers */
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#define ISP176x_HC_VERSION 0x002
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#define ISP176x_HC_HCSPARAMS 0x004
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#define ISP176x_HC_HCCPARAMS 0x008
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/* EHCI operational registers */
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#define ISP176x_HC_USBCMD 0x020
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#define ISP176x_HC_USBSTS 0x024
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#define ISP176x_HC_FRINDEX 0x02c
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#define ISP176x_HC_CONFIGFLAG 0x060
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#define ISP176x_HC_PORTSC1 0x064
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#define ISP176x_HC_ISO_PTD_DONEMAP 0x130
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#define ISP176x_HC_ISO_PTD_SKIPMAP 0x134
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#define ISP176x_HC_ISO_PTD_LASTPTD 0x138
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#define ISP176x_HC_INT_PTD_DONEMAP 0x140
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#define ISP176x_HC_INT_PTD_SKIPMAP 0x144
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#define ISP176x_HC_INT_PTD_LASTPTD 0x148
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#define ISP176x_HC_ATL_PTD_DONEMAP 0x150
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#define ISP176x_HC_ATL_PTD_SKIPMAP 0x154
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#define ISP176x_HC_ATL_PTD_LASTPTD 0x158
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/* Configuration Register */
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#define ISP176x_HC_HW_MODE_CTRL 0x300
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#define ISP176x_HC_CHIP_ID 0x304
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#define ISP176x_HC_SCRATCH 0x308
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#define ISP176x_HC_RESET 0x30c
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#define ISP176x_HC_BUFFER_STATUS 0x334
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#define ISP176x_HC_MEMORY 0x33c
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/* Interrupt Register */
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#define ISP176x_HC_INTERRUPT 0x310
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#define ISP176x_HC_INTERRUPT_ENABLE 0x314
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#define ISP176x_HC_ISO_IRQ_MASK_OR 0x318
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#define ISP176x_HC_INT_IRQ_MASK_OR 0x31c
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#define ISP176x_HC_ATL_IRQ_MASK_OR 0x320
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#define ISP176x_HC_ISO_IRQ_MASK_AND 0x324
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#define ISP176x_HC_INT_IRQ_MASK_AND 0x328
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#define ISP176x_HC_ATL_IRQ_MASK_AND 0x32c
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#define ISP176x_HC_OTG_CTRL 0x374
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#define ISP176x_HC_OTG_CTRL_SET 0x374
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#define ISP176x_HC_OTG_CTRL_CLEAR 0x376
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enum isp176x_host_controller_fields {
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/* HC_PORTSC1 */
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PORT_OWNER, PORT_POWER, PORT_LSTATUS, PORT_RESET, PORT_SUSPEND,
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PORT_RESUME, PORT_PE, PORT_CSC, PORT_CONNECT,
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/* HC_HCSPARAMS */
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HCS_PPC, HCS_N_PORTS,
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/* HC_HCCPARAMS */
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HCC_ISOC_CACHE, HCC_ISOC_THRES,
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/* HC_USBCMD */
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CMD_LRESET, CMD_RESET, CMD_RUN,
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/* HC_USBSTS */
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STS_PCD,
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/* HC_FRINDEX */
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HC_FRINDEX,
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/* HC_CONFIGFLAG */
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FLAG_CF,
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/* ISO/INT/ATL PTD */
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HC_ISO_PTD_DONEMAP, HC_ISO_PTD_SKIPMAP, HC_ISO_PTD_LASTPTD,
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HC_INT_PTD_DONEMAP, HC_INT_PTD_SKIPMAP, HC_INT_PTD_LASTPTD,
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HC_ATL_PTD_DONEMAP, HC_ATL_PTD_SKIPMAP, HC_ATL_PTD_LASTPTD,
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/* HC_HW_MODE_CTRL */
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ALL_ATX_RESET, HW_ANA_DIGI_OC, HW_DEV_DMA, HW_COMN_IRQ, HW_COMN_DMA,
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HW_DATA_BUS_WIDTH, HW_DACK_POL_HIGH, HW_DREQ_POL_HIGH, HW_INTR_HIGH_ACT,
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HW_INTF_LOCK, HW_INTR_EDGE_TRIG, HW_GLOBAL_INTR_EN,
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/* HC_CHIP_ID */
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HC_CHIP_ID_HIGH, HC_CHIP_ID_LOW, HC_CHIP_REV,
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/* HC_SCRATCH */
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HC_SCRATCH,
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/* HC_RESET */
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SW_RESET_RESET_ATX, SW_RESET_RESET_HC, SW_RESET_RESET_ALL,
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/* HC_BUFFER_STATUS */
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ISO_BUF_FILL, INT_BUF_FILL, ATL_BUF_FILL,
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/* HC_MEMORY */
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MEM_BANK_SEL, MEM_START_ADDR,
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/* HC_DATA */
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HC_DATA,
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/* HC_INTERRUPT */
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HC_INTERRUPT,
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/* HC_INTERRUPT_ENABLE */
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HC_INT_IRQ_ENABLE, HC_ATL_IRQ_ENABLE,
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/* INTERRUPT MASKS */
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HC_ISO_IRQ_MASK_OR, HC_INT_IRQ_MASK_OR, HC_ATL_IRQ_MASK_OR,
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HC_ISO_IRQ_MASK_AND, HC_INT_IRQ_MASK_AND, HC_ATL_IRQ_MASK_AND,
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/* HW_OTG_CTRL_SET */
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HW_OTG_DISABLE, HW_SW_SEL_HC_DC, HW_VBUS_DRV, HW_SEL_CP_EXT,
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HW_DM_PULLDOWN, HW_DP_PULLDOWN, HW_DP_PULLUP, HW_HC_2_DIS,
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/* HW_OTG_CTRL_CLR */
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HW_OTG_DISABLE_CLEAR, HW_SW_SEL_HC_DC_CLEAR, HW_VBUS_DRV_CLEAR,
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HW_SEL_CP_EXT_CLEAR, HW_DM_PULLDOWN_CLEAR, HW_DP_PULLDOWN_CLEAR,
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HW_DP_PULLUP_CLEAR, HW_HC_2_DIS_CLEAR,
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/* Last element */
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HC_FIELD_MAX,
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};
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/* ISP1763 */
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/* EHCI operational registers */
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#define ISP1763_HC_USBCMD 0x8c
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#define ISP1763_HC_USBSTS 0x90
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#define ISP1763_HC_FRINDEX 0x98
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#define ISP1763_HC_CONFIGFLAG 0x9c
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#define ISP1763_HC_PORTSC1 0xa0
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#define ISP1763_HC_ISO_PTD_DONEMAP 0xa4
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#define ISP1763_HC_ISO_PTD_SKIPMAP 0xa6
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#define ISP1763_HC_ISO_PTD_LASTPTD 0xa8
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#define ISP1763_HC_INT_PTD_DONEMAP 0xaa
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#define ISP1763_HC_INT_PTD_SKIPMAP 0xac
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#define ISP1763_HC_INT_PTD_LASTPTD 0xae
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#define ISP1763_HC_ATL_PTD_DONEMAP 0xb0
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#define ISP1763_HC_ATL_PTD_SKIPMAP 0xb2
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#define ISP1763_HC_ATL_PTD_LASTPTD 0xb4
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/* Configuration Register */
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#define ISP1763_HC_HW_MODE_CTRL 0xb6
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#define ISP1763_HC_CHIP_REV 0x70
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#define ISP1763_HC_CHIP_ID 0x72
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#define ISP1763_HC_SCRATCH 0x78
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#define ISP1763_HC_RESET 0xb8
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#define ISP1763_HC_BUFFER_STATUS 0xba
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#define ISP1763_HC_MEMORY 0xc4
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#define ISP1763_HC_DATA 0xc6
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/* Interrupt Register */
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#define ISP1763_HC_INTERRUPT 0xd4
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#define ISP1763_HC_INTERRUPT_ENABLE 0xd6
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#define ISP1763_HC_ISO_IRQ_MASK_OR 0xd8
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#define ISP1763_HC_INT_IRQ_MASK_OR 0xda
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#define ISP1763_HC_ATL_IRQ_MASK_OR 0xdc
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#define ISP1763_HC_ISO_IRQ_MASK_AND 0xde
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#define ISP1763_HC_INT_IRQ_MASK_AND 0xe0
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#define ISP1763_HC_ATL_IRQ_MASK_AND 0xe2
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#define ISP1763_HC_OTG_CTRL_SET 0xe4
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#define ISP1763_HC_OTG_CTRL_CLEAR 0xe6
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/* -----------------------------------------------------------------------------
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* Peripheral Controller
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*/
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#define DC_IEPTX(n) (1 << (11 + 2 * (n)))
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#define DC_IEPRX(n) (1 << (10 + 2 * (n)))
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#define DC_IEPRXTX(n) (3 << (10 + 2 * (n)))
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#define ISP176x_DC_CDBGMOD_ACK BIT(6)
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#define ISP176x_DC_DDBGMODIN_ACK BIT(4)
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#define ISP176x_DC_DDBGMODOUT_ACK BIT(2)
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#define ISP176x_DC_IEP0SETUP BIT(8)
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#define ISP176x_DC_IEVBUS BIT(7)
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#define ISP176x_DC_IEHS_STA BIT(5)
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#define ISP176x_DC_IERESM BIT(4)
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#define ISP176x_DC_IESUSP BIT(3)
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#define ISP176x_DC_IEBRST BIT(0)
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#define ISP176x_HW_OTG_DISABLE_CLEAR BIT(26)
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#define ISP176x_HW_SW_SEL_HC_DC_CLEAR BIT(23)
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#define ISP176x_HW_VBUS_DRV_CLEAR BIT(20)
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#define ISP176x_HW_SEL_CP_EXT_CLEAR BIT(19)
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#define ISP176x_HW_DM_PULLDOWN_CLEAR BIT(18)
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#define ISP176x_HW_DP_PULLDOWN_CLEAR BIT(17)
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#define ISP176x_HW_DP_PULLUP_CLEAR BIT(16)
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#define ISP176x_HW_OTG_DISABLE BIT(10)
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#define ISP176x_HW_SW_SEL_HC_DC BIT(7)
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#define ISP176x_HW_VBUS_DRV BIT(4)
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#define ISP176x_HW_SEL_CP_EXT BIT(3)
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#define ISP176x_HW_DM_PULLDOWN BIT(2)
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#define ISP176x_HW_DP_PULLDOWN BIT(1)
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#define ISP176x_HW_DP_PULLUP BIT(0)
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#define ISP176x_DC_ENDPTYP_ISOC 0x01
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#define ISP176x_DC_ENDPTYP_BULK 0x02
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#define ISP176x_DC_ENDPTYP_INTERRUPT 0x03
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/* Initialization Registers */
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#define ISP176x_DC_ADDRESS 0x0200
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#define ISP176x_DC_MODE 0x020c
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#define ISP176x_DC_INTCONF 0x0210
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#define ISP176x_DC_DEBUG 0x0212
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#define ISP176x_DC_INTENABLE 0x0214
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/* Data Flow Registers */
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#define ISP176x_DC_EPMAXPKTSZ 0x0204
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#define ISP176x_DC_EPTYPE 0x0208
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#define ISP176x_DC_BUFLEN 0x021c
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#define ISP176x_DC_BUFSTAT 0x021e
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#define ISP176x_DC_DATAPORT 0x0220
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#define ISP176x_DC_CTRLFUNC 0x0228
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#define ISP176x_DC_EPINDEX 0x022c
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/* DMA Registers */
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#define ISP176x_DC_DMACMD 0x0230
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#define ISP176x_DC_DMATXCOUNT 0x0234
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#define ISP176x_DC_DMACONF 0x0238
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#define ISP176x_DC_DMAHW 0x023c
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#define ISP176x_DC_DMAINTREASON 0x0250
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#define ISP176x_DC_DMAINTEN 0x0254
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#define ISP176x_DC_DMAEP 0x0258
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#define ISP176x_DC_DMABURSTCOUNT 0x0264
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/* General Registers */
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#define ISP176x_DC_INTERRUPT 0x0218
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#define ISP176x_DC_CHIPID 0x0270
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#define ISP176x_DC_FRAMENUM 0x0274
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#define ISP176x_DC_SCRATCH 0x0278
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#define ISP176x_DC_UNLOCKDEV 0x027c
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#define ISP176x_DC_INTPULSEWIDTH 0x0280
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#define ISP176x_DC_TESTMODE 0x0284
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enum isp176x_device_controller_fields {
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/* DC_ADDRESS */
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DC_DEVEN, DC_DEVADDR,
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/* DC_MODE */
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DC_VBUSSTAT, DC_SFRESET, DC_GLINTENA,
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/* DC_INTCONF */
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DC_CDBGMOD_ACK, DC_DDBGMODIN_ACK, DC_DDBGMODOUT_ACK, DC_INTPOL,
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/* DC_INTENABLE */
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DC_IEPRXTX_7, DC_IEPRXTX_6, DC_IEPRXTX_5, DC_IEPRXTX_4, DC_IEPRXTX_3,
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DC_IEPRXTX_2, DC_IEPRXTX_1, DC_IEPRXTX_0,
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DC_IEP0SETUP, DC_IEVBUS, DC_IEHS_STA, DC_IERESM, DC_IESUSP, DC_IEBRST,
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/* DC_EPINDEX */
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DC_EP0SETUP, DC_ENDPIDX, DC_EPDIR,
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/* DC_CTRLFUNC */
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DC_CLBUF, DC_VENDP, DC_DSEN, DC_STATUS, DC_STALL,
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/* DC_BUFLEN */
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DC_BUFLEN,
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/* DC_EPMAXPKTSZ */
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DC_FFOSZ,
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/* DC_EPTYPE */
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DC_EPENABLE, DC_ENDPTYP,
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/* DC_FRAMENUM */
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DC_FRAMENUM, DC_UFRAMENUM,
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/* DC_CHIP_ID */
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DC_CHIP_ID_HIGH, DC_CHIP_ID_LOW,
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/* DC_SCRATCH */
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DC_SCRATCH,
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/* Last element */
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DC_FIELD_MAX,
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};
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/* ISP1763 */
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/* Initialization Registers */
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#define ISP1763_DC_ADDRESS 0x00
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#define ISP1763_DC_MODE 0x0c
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#define ISP1763_DC_INTCONF 0x10
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#define ISP1763_DC_INTENABLE 0x14
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/* Data Flow Registers */
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#define ISP1763_DC_EPMAXPKTSZ 0x04
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#define ISP1763_DC_EPTYPE 0x08
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#define ISP1763_DC_BUFLEN 0x1c
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#define ISP1763_DC_BUFSTAT 0x1e
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#define ISP1763_DC_DATAPORT 0x20
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#define ISP1763_DC_CTRLFUNC 0x28
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#define ISP1763_DC_EPINDEX 0x2c
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/* DMA Registers */
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#define ISP1763_DC_DMACMD 0x30
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#define ISP1763_DC_DMATXCOUNT 0x34
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#define ISP1763_DC_DMACONF 0x38
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#define ISP1763_DC_DMAHW 0x3c
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#define ISP1763_DC_DMAINTREASON 0x50
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#define ISP1763_DC_DMAINTEN 0x54
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#define ISP1763_DC_DMAEP 0x58
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#define ISP1763_DC_DMABURSTCOUNT 0x64
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/* General Registers */
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#define ISP1763_DC_INTERRUPT 0x18
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#define ISP1763_DC_CHIPID_LOW 0x70
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#define ISP1763_DC_CHIPID_HIGH 0x72
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#define ISP1763_DC_FRAMENUM 0x74
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#define ISP1763_DC_SCRATCH 0x78
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#define ISP1763_DC_UNLOCKDEV 0x7c
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#define ISP1763_DC_INTPULSEWIDTH 0x80
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#define ISP1763_DC_TESTMODE 0x84
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#endif
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