751 lines
21 KiB
C
751 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (C) 2014-2015 Broadcom Corporation
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#include <linux/debugfs.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/timer.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "cygnus-ssp.h"
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/* Register offset needed for ASoC PCM module */
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#define INTH_R5F_STATUS_OFFSET 0x040
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#define INTH_R5F_CLEAR_OFFSET 0x048
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#define INTH_R5F_MASK_SET_OFFSET 0x050
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#define INTH_R5F_MASK_CLEAR_OFFSET 0x054
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#define BF_REARM_FREE_MARK_OFFSET 0x344
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#define BF_REARM_FULL_MARK_OFFSET 0x348
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/* Ring Buffer Ctrl Regs --- Start */
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/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_RDADDR_REG_BASE */
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#define SRC_RBUF_0_RDADDR_OFFSET 0x500
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#define SRC_RBUF_1_RDADDR_OFFSET 0x518
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#define SRC_RBUF_2_RDADDR_OFFSET 0x530
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#define SRC_RBUF_3_RDADDR_OFFSET 0x548
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#define SRC_RBUF_4_RDADDR_OFFSET 0x560
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#define SRC_RBUF_5_RDADDR_OFFSET 0x578
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#define SRC_RBUF_6_RDADDR_OFFSET 0x590
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/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_WRADDR_REG_BASE */
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#define SRC_RBUF_0_WRADDR_OFFSET 0x504
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#define SRC_RBUF_1_WRADDR_OFFSET 0x51c
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#define SRC_RBUF_2_WRADDR_OFFSET 0x534
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#define SRC_RBUF_3_WRADDR_OFFSET 0x54c
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#define SRC_RBUF_4_WRADDR_OFFSET 0x564
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#define SRC_RBUF_5_WRADDR_OFFSET 0x57c
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#define SRC_RBUF_6_WRADDR_OFFSET 0x594
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/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_BASEADDR_REG_BASE */
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#define SRC_RBUF_0_BASEADDR_OFFSET 0x508
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#define SRC_RBUF_1_BASEADDR_OFFSET 0x520
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#define SRC_RBUF_2_BASEADDR_OFFSET 0x538
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#define SRC_RBUF_3_BASEADDR_OFFSET 0x550
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#define SRC_RBUF_4_BASEADDR_OFFSET 0x568
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#define SRC_RBUF_5_BASEADDR_OFFSET 0x580
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#define SRC_RBUF_6_BASEADDR_OFFSET 0x598
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/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_ENDADDR_REG_BASE */
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#define SRC_RBUF_0_ENDADDR_OFFSET 0x50c
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#define SRC_RBUF_1_ENDADDR_OFFSET 0x524
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#define SRC_RBUF_2_ENDADDR_OFFSET 0x53c
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#define SRC_RBUF_3_ENDADDR_OFFSET 0x554
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#define SRC_RBUF_4_ENDADDR_OFFSET 0x56c
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#define SRC_RBUF_5_ENDADDR_OFFSET 0x584
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#define SRC_RBUF_6_ENDADDR_OFFSET 0x59c
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/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_FREE_MARK_REG_BASE */
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#define SRC_RBUF_0_FREE_MARK_OFFSET 0x510
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#define SRC_RBUF_1_FREE_MARK_OFFSET 0x528
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#define SRC_RBUF_2_FREE_MARK_OFFSET 0x540
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#define SRC_RBUF_3_FREE_MARK_OFFSET 0x558
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#define SRC_RBUF_4_FREE_MARK_OFFSET 0x570
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#define SRC_RBUF_5_FREE_MARK_OFFSET 0x588
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#define SRC_RBUF_6_FREE_MARK_OFFSET 0x5a0
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/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_RDADDR_REG_BASE */
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#define DST_RBUF_0_RDADDR_OFFSET 0x5c0
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#define DST_RBUF_1_RDADDR_OFFSET 0x5d8
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#define DST_RBUF_2_RDADDR_OFFSET 0x5f0
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#define DST_RBUF_3_RDADDR_OFFSET 0x608
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#define DST_RBUF_4_RDADDR_OFFSET 0x620
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#define DST_RBUF_5_RDADDR_OFFSET 0x638
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/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_WRADDR_REG_BASE */
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#define DST_RBUF_0_WRADDR_OFFSET 0x5c4
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#define DST_RBUF_1_WRADDR_OFFSET 0x5dc
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#define DST_RBUF_2_WRADDR_OFFSET 0x5f4
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#define DST_RBUF_3_WRADDR_OFFSET 0x60c
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#define DST_RBUF_4_WRADDR_OFFSET 0x624
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#define DST_RBUF_5_WRADDR_OFFSET 0x63c
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/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_BASEADDR_REG_BASE */
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#define DST_RBUF_0_BASEADDR_OFFSET 0x5c8
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#define DST_RBUF_1_BASEADDR_OFFSET 0x5e0
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#define DST_RBUF_2_BASEADDR_OFFSET 0x5f8
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#define DST_RBUF_3_BASEADDR_OFFSET 0x610
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#define DST_RBUF_4_BASEADDR_OFFSET 0x628
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#define DST_RBUF_5_BASEADDR_OFFSET 0x640
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/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_ENDADDR_REG_BASE */
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#define DST_RBUF_0_ENDADDR_OFFSET 0x5cc
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#define DST_RBUF_1_ENDADDR_OFFSET 0x5e4
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#define DST_RBUF_2_ENDADDR_OFFSET 0x5fc
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#define DST_RBUF_3_ENDADDR_OFFSET 0x614
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#define DST_RBUF_4_ENDADDR_OFFSET 0x62c
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#define DST_RBUF_5_ENDADDR_OFFSET 0x644
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/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_FULL_MARK_REG_BASE */
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#define DST_RBUF_0_FULL_MARK_OFFSET 0x5d0
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#define DST_RBUF_1_FULL_MARK_OFFSET 0x5e8
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#define DST_RBUF_2_FULL_MARK_OFFSET 0x600
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#define DST_RBUF_3_FULL_MARK_OFFSET 0x618
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#define DST_RBUF_4_FULL_MARK_OFFSET 0x630
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#define DST_RBUF_5_FULL_MARK_OFFSET 0x648
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/* Ring Buffer Ctrl Regs --- End */
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/* Error Status Regs --- Start */
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/* AUD_FMM_BF_ESR_ESRX_STATUS_REG_BASE */
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#define ESR0_STATUS_OFFSET 0x900
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#define ESR1_STATUS_OFFSET 0x918
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#define ESR2_STATUS_OFFSET 0x930
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#define ESR3_STATUS_OFFSET 0x948
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#define ESR4_STATUS_OFFSET 0x960
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/* AUD_FMM_BF_ESR_ESRX_STATUS_CLEAR_REG_BASE */
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#define ESR0_STATUS_CLR_OFFSET 0x908
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#define ESR1_STATUS_CLR_OFFSET 0x920
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#define ESR2_STATUS_CLR_OFFSET 0x938
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#define ESR3_STATUS_CLR_OFFSET 0x950
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#define ESR4_STATUS_CLR_OFFSET 0x968
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/* AUD_FMM_BF_ESR_ESRX_MASK_REG_BASE */
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#define ESR0_MASK_STATUS_OFFSET 0x90c
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#define ESR1_MASK_STATUS_OFFSET 0x924
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#define ESR2_MASK_STATUS_OFFSET 0x93c
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#define ESR3_MASK_STATUS_OFFSET 0x954
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#define ESR4_MASK_STATUS_OFFSET 0x96c
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/* AUD_FMM_BF_ESR_ESRX_MASK_SET_REG_BASE */
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#define ESR0_MASK_SET_OFFSET 0x910
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#define ESR1_MASK_SET_OFFSET 0x928
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#define ESR2_MASK_SET_OFFSET 0x940
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#define ESR3_MASK_SET_OFFSET 0x958
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#define ESR4_MASK_SET_OFFSET 0x970
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/* AUD_FMM_BF_ESR_ESRX_MASK_CLEAR_REG_BASE */
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#define ESR0_MASK_CLR_OFFSET 0x914
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#define ESR1_MASK_CLR_OFFSET 0x92c
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#define ESR2_MASK_CLR_OFFSET 0x944
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#define ESR3_MASK_CLR_OFFSET 0x95c
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#define ESR4_MASK_CLR_OFFSET 0x974
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/* Error Status Regs --- End */
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#define R5F_ESR0_SHIFT 0 /* esr0 = fifo underflow */
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#define R5F_ESR1_SHIFT 1 /* esr1 = ringbuf underflow */
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#define R5F_ESR2_SHIFT 2 /* esr2 = ringbuf overflow */
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#define R5F_ESR3_SHIFT 3 /* esr3 = freemark */
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#define R5F_ESR4_SHIFT 4 /* esr4 = fullmark */
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/* Mask for R5F register. Set all relevant interrupt for playback handler */
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#define ANY_PLAYBACK_IRQ (BIT(R5F_ESR0_SHIFT) | \
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BIT(R5F_ESR1_SHIFT) | \
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BIT(R5F_ESR3_SHIFT))
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/* Mask for R5F register. Set all relevant interrupt for capture handler */
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#define ANY_CAPTURE_IRQ (BIT(R5F_ESR2_SHIFT) | BIT(R5F_ESR4_SHIFT))
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/*
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* PERIOD_BYTES_MIN is the number of bytes to at which the interrupt will tick.
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* This number should be a multiple of 256. Minimum value is 256
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*/
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#define PERIOD_BYTES_MIN 0x100
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static const struct snd_pcm_hardware cygnus_pcm_hw = {
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.info = SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_INTERLEAVED,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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/* A period is basically an interrupt */
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.period_bytes_min = PERIOD_BYTES_MIN,
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.period_bytes_max = 0x10000,
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/* period_min/max gives range of approx interrupts per buffer */
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.periods_min = 2,
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.periods_max = 8,
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/*
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* maximum buffer size in bytes = period_bytes_max * periods_max
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* We allocate this amount of data for each enabled channel
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*/
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.buffer_bytes_max = 4 * 0x8000,
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};
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static u64 cygnus_dma_dmamask = DMA_BIT_MASK(32);
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static struct cygnus_aio_port *cygnus_dai_get_dma_data(
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struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
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return snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(soc_runtime, 0), substream);
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}
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static void ringbuf_set_initial(void __iomem *audio_io,
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struct ringbuf_regs *p_rbuf,
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bool is_playback,
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u32 start,
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u32 periodsize,
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u32 bufsize)
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{
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u32 initial_rd;
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u32 initial_wr;
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u32 end;
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u32 fmark_val; /* free or full mark */
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p_rbuf->period_bytes = periodsize;
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p_rbuf->buf_size = bufsize;
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if (is_playback) {
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/* Set the pointers to indicate full (flip uppermost bit) */
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initial_rd = start;
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initial_wr = initial_rd ^ BIT(31);
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} else {
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/* Set the pointers to indicate empty */
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initial_wr = start;
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initial_rd = initial_wr;
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}
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end = start + bufsize - 1;
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/*
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* The interrupt will fire when free/full mark is *exceeded*
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* The fmark value must be multiple of PERIOD_BYTES_MIN so set fmark
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* to be PERIOD_BYTES_MIN less than the period size.
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*/
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fmark_val = periodsize - PERIOD_BYTES_MIN;
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writel(start, audio_io + p_rbuf->baseaddr);
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writel(end, audio_io + p_rbuf->endaddr);
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writel(fmark_val, audio_io + p_rbuf->fmark);
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writel(initial_rd, audio_io + p_rbuf->rdaddr);
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writel(initial_wr, audio_io + p_rbuf->wraddr);
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}
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static int configure_ringbuf_regs(struct snd_pcm_substream *substream)
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{
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struct cygnus_aio_port *aio;
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struct ringbuf_regs *p_rbuf;
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int status = 0;
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aio = cygnus_dai_get_dma_data(substream);
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/* Map the ssp portnum to a set of ring buffers. */
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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p_rbuf = &aio->play_rb_regs;
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switch (aio->portnum) {
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case 0:
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*p_rbuf = RINGBUF_REG_PLAYBACK(0);
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break;
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case 1:
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*p_rbuf = RINGBUF_REG_PLAYBACK(2);
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break;
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case 2:
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*p_rbuf = RINGBUF_REG_PLAYBACK(4);
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break;
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case 3: /* SPDIF */
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*p_rbuf = RINGBUF_REG_PLAYBACK(6);
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break;
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default:
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status = -EINVAL;
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}
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} else {
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p_rbuf = &aio->capture_rb_regs;
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switch (aio->portnum) {
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case 0:
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*p_rbuf = RINGBUF_REG_CAPTURE(0);
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break;
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case 1:
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*p_rbuf = RINGBUF_REG_CAPTURE(2);
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break;
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case 2:
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*p_rbuf = RINGBUF_REG_CAPTURE(4);
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break;
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default:
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status = -EINVAL;
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}
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}
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return status;
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}
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static struct ringbuf_regs *get_ringbuf(struct snd_pcm_substream *substream)
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{
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struct cygnus_aio_port *aio;
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struct ringbuf_regs *p_rbuf = NULL;
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aio = cygnus_dai_get_dma_data(substream);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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p_rbuf = &aio->play_rb_regs;
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else
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p_rbuf = &aio->capture_rb_regs;
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return p_rbuf;
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}
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static void enable_intr(struct snd_pcm_substream *substream)
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{
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struct cygnus_aio_port *aio;
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u32 clear_mask;
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aio = cygnus_dai_get_dma_data(substream);
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/* The port number maps to the bit position to be cleared */
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clear_mask = BIT(aio->portnum);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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/* Clear interrupt status before enabling them */
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writel(clear_mask, aio->cygaud->audio + ESR0_STATUS_CLR_OFFSET);
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writel(clear_mask, aio->cygaud->audio + ESR1_STATUS_CLR_OFFSET);
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writel(clear_mask, aio->cygaud->audio + ESR3_STATUS_CLR_OFFSET);
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/* Unmask the interrupts of the given port*/
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writel(clear_mask, aio->cygaud->audio + ESR0_MASK_CLR_OFFSET);
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writel(clear_mask, aio->cygaud->audio + ESR1_MASK_CLR_OFFSET);
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writel(clear_mask, aio->cygaud->audio + ESR3_MASK_CLR_OFFSET);
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writel(ANY_PLAYBACK_IRQ,
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aio->cygaud->audio + INTH_R5F_MASK_CLEAR_OFFSET);
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} else {
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writel(clear_mask, aio->cygaud->audio + ESR2_STATUS_CLR_OFFSET);
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writel(clear_mask, aio->cygaud->audio + ESR4_STATUS_CLR_OFFSET);
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writel(clear_mask, aio->cygaud->audio + ESR2_MASK_CLR_OFFSET);
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writel(clear_mask, aio->cygaud->audio + ESR4_MASK_CLR_OFFSET);
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writel(ANY_CAPTURE_IRQ,
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aio->cygaud->audio + INTH_R5F_MASK_CLEAR_OFFSET);
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}
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}
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static void disable_intr(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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struct cygnus_aio_port *aio;
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u32 set_mask;
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aio = cygnus_dai_get_dma_data(substream);
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dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s on port %d\n", __func__, aio->portnum);
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/* The port number maps to the bit position to be set */
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set_mask = BIT(aio->portnum);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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/* Mask the interrupts of the given port*/
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writel(set_mask, aio->cygaud->audio + ESR0_MASK_SET_OFFSET);
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writel(set_mask, aio->cygaud->audio + ESR1_MASK_SET_OFFSET);
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writel(set_mask, aio->cygaud->audio + ESR3_MASK_SET_OFFSET);
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} else {
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writel(set_mask, aio->cygaud->audio + ESR2_MASK_SET_OFFSET);
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writel(set_mask, aio->cygaud->audio + ESR4_MASK_SET_OFFSET);
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}
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}
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static int cygnus_pcm_trigger(struct snd_soc_component *component,
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struct snd_pcm_substream *substream, int cmd)
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{
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int ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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enable_intr(substream);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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disable_intr(substream);
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static void cygnus_pcm_period_elapsed(struct snd_pcm_substream *substream)
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{
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struct cygnus_aio_port *aio;
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struct ringbuf_regs *p_rbuf = NULL;
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u32 regval;
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aio = cygnus_dai_get_dma_data(substream);
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p_rbuf = get_ringbuf(substream);
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/*
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* If free/full mark interrupt occurs, provide timestamp
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* to ALSA and update appropriate idx by period_bytes
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*/
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snd_pcm_period_elapsed(substream);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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/* Set the ring buffer to full */
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regval = readl(aio->cygaud->audio + p_rbuf->rdaddr);
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regval = regval ^ BIT(31);
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writel(regval, aio->cygaud->audio + p_rbuf->wraddr);
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} else {
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/* Set the ring buffer to empty */
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regval = readl(aio->cygaud->audio + p_rbuf->wraddr);
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writel(regval, aio->cygaud->audio + p_rbuf->rdaddr);
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}
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}
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/*
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* ESR0/1/3 status Description
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* 0x1 I2S0_out port caused interrupt
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* 0x2 I2S1_out port caused interrupt
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* 0x4 I2S2_out port caused interrupt
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* 0x8 SPDIF_out port caused interrupt
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*/
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static void handle_playback_irq(struct cygnus_audio *cygaud)
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{
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void __iomem *audio_io;
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u32 port;
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u32 esr_status0, esr_status1, esr_status3;
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audio_io = cygaud->audio;
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/*
|
|
* ESR status gets updates with/without interrupts enabled.
|
|
* So, check the ESR mask, which provides interrupt enable/
|
|
* disable status and use it to determine which ESR status
|
|
* should be serviced.
|
|
*/
|
|
esr_status0 = readl(audio_io + ESR0_STATUS_OFFSET);
|
|
esr_status0 &= ~readl(audio_io + ESR0_MASK_STATUS_OFFSET);
|
|
esr_status1 = readl(audio_io + ESR1_STATUS_OFFSET);
|
|
esr_status1 &= ~readl(audio_io + ESR1_MASK_STATUS_OFFSET);
|
|
esr_status3 = readl(audio_io + ESR3_STATUS_OFFSET);
|
|
esr_status3 &= ~readl(audio_io + ESR3_MASK_STATUS_OFFSET);
|
|
|
|
for (port = 0; port < CYGNUS_MAX_PLAYBACK_PORTS; port++) {
|
|
u32 esrmask = BIT(port);
|
|
|
|
/*
|
|
* Ringbuffer or FIFO underflow
|
|
* If we get this interrupt then, it is also true that we have
|
|
* not yet responded to the freemark interrupt.
|
|
* Log a debug message. The freemark handler below will
|
|
* handle getting everything going again.
|
|
*/
|
|
if ((esrmask & esr_status1) || (esrmask & esr_status0)) {
|
|
dev_dbg(cygaud->dev,
|
|
"Underrun: esr0=0x%x, esr1=0x%x esr3=0x%x\n",
|
|
esr_status0, esr_status1, esr_status3);
|
|
}
|
|
|
|
/*
|
|
* Freemark is hit. This is the normal interrupt.
|
|
* In typical operation the read and write regs will be equal
|
|
*/
|
|
if (esrmask & esr_status3) {
|
|
struct snd_pcm_substream *playstr;
|
|
|
|
playstr = cygaud->portinfo[port].play_stream;
|
|
cygnus_pcm_period_elapsed(playstr);
|
|
}
|
|
}
|
|
|
|
/* Clear ESR interrupt */
|
|
writel(esr_status0, audio_io + ESR0_STATUS_CLR_OFFSET);
|
|
writel(esr_status1, audio_io + ESR1_STATUS_CLR_OFFSET);
|
|
writel(esr_status3, audio_io + ESR3_STATUS_CLR_OFFSET);
|
|
/* Rearm freemark logic by writing 1 to the correct bit */
|
|
writel(esr_status3, audio_io + BF_REARM_FREE_MARK_OFFSET);
|
|
}
|
|
|
|
/*
|
|
* ESR2/4 status Description
|
|
* 0x1 I2S0_in port caused interrupt
|
|
* 0x2 I2S1_in port caused interrupt
|
|
* 0x4 I2S2_in port caused interrupt
|
|
*/
|
|
static void handle_capture_irq(struct cygnus_audio *cygaud)
|
|
{
|
|
void __iomem *audio_io;
|
|
u32 port;
|
|
u32 esr_status2, esr_status4;
|
|
|
|
audio_io = cygaud->audio;
|
|
|
|
/*
|
|
* ESR status gets updates with/without interrupts enabled.
|
|
* So, check the ESR mask, which provides interrupt enable/
|
|
* disable status and use it to determine which ESR status
|
|
* should be serviced.
|
|
*/
|
|
esr_status2 = readl(audio_io + ESR2_STATUS_OFFSET);
|
|
esr_status2 &= ~readl(audio_io + ESR2_MASK_STATUS_OFFSET);
|
|
esr_status4 = readl(audio_io + ESR4_STATUS_OFFSET);
|
|
esr_status4 &= ~readl(audio_io + ESR4_MASK_STATUS_OFFSET);
|
|
|
|
for (port = 0; port < CYGNUS_MAX_CAPTURE_PORTS; port++) {
|
|
u32 esrmask = BIT(port);
|
|
|
|
/*
|
|
* Ringbuffer or FIFO overflow
|
|
* If we get this interrupt then, it is also true that we have
|
|
* not yet responded to the fullmark interrupt.
|
|
* Log a debug message. The fullmark handler below will
|
|
* handle getting everything going again.
|
|
*/
|
|
if (esrmask & esr_status2)
|
|
dev_dbg(cygaud->dev,
|
|
"Overflow: esr2=0x%x\n", esr_status2);
|
|
|
|
if (esrmask & esr_status4) {
|
|
struct snd_pcm_substream *capstr;
|
|
|
|
capstr = cygaud->portinfo[port].capture_stream;
|
|
cygnus_pcm_period_elapsed(capstr);
|
|
}
|
|
}
|
|
|
|
writel(esr_status2, audio_io + ESR2_STATUS_CLR_OFFSET);
|
|
writel(esr_status4, audio_io + ESR4_STATUS_CLR_OFFSET);
|
|
/* Rearm fullmark logic by writing 1 to the correct bit */
|
|
writel(esr_status4, audio_io + BF_REARM_FULL_MARK_OFFSET);
|
|
}
|
|
|
|
static irqreturn_t cygnus_dma_irq(int irq, void *data)
|
|
{
|
|
u32 r5_status;
|
|
struct cygnus_audio *cygaud = data;
|
|
|
|
/*
|
|
* R5 status bits Description
|
|
* 0 ESR0 (playback FIFO interrupt)
|
|
* 1 ESR1 (playback rbuf interrupt)
|
|
* 2 ESR2 (capture rbuf interrupt)
|
|
* 3 ESR3 (Freemark play. interrupt)
|
|
* 4 ESR4 (Fullmark capt. interrupt)
|
|
*/
|
|
r5_status = readl(cygaud->audio + INTH_R5F_STATUS_OFFSET);
|
|
|
|
if (!(r5_status & (ANY_PLAYBACK_IRQ | ANY_CAPTURE_IRQ)))
|
|
return IRQ_NONE;
|
|
|
|
/* If playback interrupt happened */
|
|
if (ANY_PLAYBACK_IRQ & r5_status) {
|
|
handle_playback_irq(cygaud);
|
|
writel(ANY_PLAYBACK_IRQ & r5_status,
|
|
cygaud->audio + INTH_R5F_CLEAR_OFFSET);
|
|
}
|
|
|
|
/* If capture interrupt happened */
|
|
if (ANY_CAPTURE_IRQ & r5_status) {
|
|
handle_capture_irq(cygaud);
|
|
writel(ANY_CAPTURE_IRQ & r5_status,
|
|
cygaud->audio + INTH_R5F_CLEAR_OFFSET);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int cygnus_pcm_open(struct snd_soc_component *component,
|
|
struct snd_pcm_substream *substream)
|
|
{
|
|
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
struct cygnus_aio_port *aio;
|
|
int ret;
|
|
|
|
aio = cygnus_dai_get_dma_data(substream);
|
|
if (!aio)
|
|
return -ENODEV;
|
|
|
|
dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);
|
|
|
|
snd_soc_set_runtime_hwparams(substream, &cygnus_pcm_hw);
|
|
|
|
ret = snd_pcm_hw_constraint_step(runtime, 0,
|
|
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, PERIOD_BYTES_MIN);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = snd_pcm_hw_constraint_step(runtime, 0,
|
|
SNDRV_PCM_HW_PARAM_BUFFER_BYTES, PERIOD_BYTES_MIN);
|
|
if (ret < 0)
|
|
return ret;
|
|
/*
|
|
* Keep track of which substream belongs to which port.
|
|
* This info is needed by snd_pcm_period_elapsed() in irq_handler
|
|
*/
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
aio->play_stream = substream;
|
|
else
|
|
aio->capture_stream = substream;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cygnus_pcm_close(struct snd_soc_component *component,
|
|
struct snd_pcm_substream *substream)
|
|
{
|
|
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
|
|
struct cygnus_aio_port *aio;
|
|
|
|
aio = cygnus_dai_get_dma_data(substream);
|
|
|
|
dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
aio->play_stream = NULL;
|
|
else
|
|
aio->capture_stream = NULL;
|
|
|
|
if (!aio->play_stream && !aio->capture_stream)
|
|
dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "freed port %d\n", aio->portnum);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cygnus_pcm_prepare(struct snd_soc_component *component,
|
|
struct snd_pcm_substream *substream)
|
|
{
|
|
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
struct cygnus_aio_port *aio;
|
|
unsigned long bufsize, periodsize;
|
|
bool is_play;
|
|
u32 start;
|
|
struct ringbuf_regs *p_rbuf = NULL;
|
|
|
|
aio = cygnus_dai_get_dma_data(substream);
|
|
dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);
|
|
|
|
bufsize = snd_pcm_lib_buffer_bytes(substream);
|
|
periodsize = snd_pcm_lib_period_bytes(substream);
|
|
|
|
dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s (buf_size %lu) (period_size %lu)\n",
|
|
__func__, bufsize, periodsize);
|
|
|
|
configure_ringbuf_regs(substream);
|
|
|
|
p_rbuf = get_ringbuf(substream);
|
|
|
|
start = runtime->dma_addr;
|
|
|
|
is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 1 : 0;
|
|
|
|
ringbuf_set_initial(aio->cygaud->audio, p_rbuf, is_play, start,
|
|
periodsize, bufsize);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static snd_pcm_uframes_t cygnus_pcm_pointer(struct snd_soc_component *component,
|
|
struct snd_pcm_substream *substream)
|
|
{
|
|
struct cygnus_aio_port *aio;
|
|
unsigned int res = 0, cur = 0, base = 0;
|
|
struct ringbuf_regs *p_rbuf = NULL;
|
|
|
|
aio = cygnus_dai_get_dma_data(substream);
|
|
|
|
/*
|
|
* Get the offset of the current read (for playack) or write
|
|
* index (for capture). Report this value back to the asoc framework.
|
|
*/
|
|
p_rbuf = get_ringbuf(substream);
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
cur = readl(aio->cygaud->audio + p_rbuf->rdaddr);
|
|
else
|
|
cur = readl(aio->cygaud->audio + p_rbuf->wraddr);
|
|
|
|
base = readl(aio->cygaud->audio + p_rbuf->baseaddr);
|
|
|
|
/*
|
|
* Mask off the MSB of the rdaddr,wraddr and baseaddr
|
|
* since MSB is not part of the address
|
|
*/
|
|
res = (cur & 0x7fffffff) - (base & 0x7fffffff);
|
|
|
|
return bytes_to_frames(substream->runtime, res);
|
|
}
|
|
|
|
static int cygnus_dma_new(struct snd_soc_component *component,
|
|
struct snd_soc_pcm_runtime *rtd)
|
|
{
|
|
size_t size = cygnus_pcm_hw.buffer_bytes_max;
|
|
struct snd_card *card = rtd->card->snd_card;
|
|
|
|
if (!card->dev->dma_mask)
|
|
card->dev->dma_mask = &cygnus_dma_dmamask;
|
|
if (!card->dev->coherent_dma_mask)
|
|
card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
|
|
|
|
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
|
|
card->dev, size, size);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct snd_soc_component_driver cygnus_soc_platform = {
|
|
.open = cygnus_pcm_open,
|
|
.close = cygnus_pcm_close,
|
|
.prepare = cygnus_pcm_prepare,
|
|
.trigger = cygnus_pcm_trigger,
|
|
.pointer = cygnus_pcm_pointer,
|
|
.pcm_construct = cygnus_dma_new,
|
|
};
|
|
|
|
int cygnus_soc_platform_register(struct device *dev,
|
|
struct cygnus_audio *cygaud)
|
|
{
|
|
int rc;
|
|
|
|
dev_dbg(dev, "%s Enter\n", __func__);
|
|
|
|
rc = devm_request_irq(dev, cygaud->irq_num, cygnus_dma_irq,
|
|
IRQF_SHARED, "cygnus-audio", cygaud);
|
|
if (rc) {
|
|
dev_err(dev, "%s request_irq error %d\n", __func__, rc);
|
|
return rc;
|
|
}
|
|
|
|
rc = devm_snd_soc_register_component(dev, &cygnus_soc_platform,
|
|
NULL, 0);
|
|
if (rc) {
|
|
dev_err(dev, "%s failed\n", __func__);
|
|
return rc;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cygnus_soc_platform_unregister(struct device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Broadcom");
|
|
MODULE_DESCRIPTION("Cygnus ASoC PCM module");
|