491 lines
12 KiB
C
491 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Clock Tree for the Texas Instruments TLV320AIC32x4
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*
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* Copyright 2019 Annaliese McDermond
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*
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* Author: Annaliese McDermond <nh6z@nh6z.net>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/regmap.h>
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#include <linux/device.h>
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#include "tlv320aic32x4.h"
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#define to_clk_aic32x4(_hw) container_of(_hw, struct clk_aic32x4, hw)
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struct clk_aic32x4 {
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struct clk_hw hw;
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struct device *dev;
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struct regmap *regmap;
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unsigned int reg;
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};
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/*
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* struct clk_aic32x4_pll_muldiv - Multiplier/divider settings
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* @p: Divider
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* @r: first multiplier
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* @j: integer part of second multiplier
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* @d: decimal part of second multiplier
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*/
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struct clk_aic32x4_pll_muldiv {
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u8 p;
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u16 r;
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u8 j;
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u16 d;
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};
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struct aic32x4_clkdesc {
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const char *name;
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const char * const *parent_names;
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unsigned int num_parents;
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const struct clk_ops *ops;
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unsigned int reg;
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};
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static int clk_aic32x4_pll_prepare(struct clk_hw *hw)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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return regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
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AIC32X4_PLLEN, AIC32X4_PLLEN);
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}
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static void clk_aic32x4_pll_unprepare(struct clk_hw *hw)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
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AIC32X4_PLLEN, 0);
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}
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static int clk_aic32x4_pll_is_prepared(struct clk_hw *hw)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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unsigned int val;
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int ret;
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ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
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if (ret < 0)
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return ret;
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return !!(val & AIC32X4_PLLEN);
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}
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static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll,
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struct clk_aic32x4_pll_muldiv *settings)
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{
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/* Change to use regmap_bulk_read? */
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unsigned int val;
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int ret;
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ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
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if (ret < 0)
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return ret;
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settings->r = val & AIC32X4_PLL_R_MASK;
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settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT;
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ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val);
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if (ret < 0)
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return ret;
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settings->j = val;
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ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val);
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if (ret < 0)
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return ret;
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settings->d = val << 8;
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ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val);
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if (ret < 0)
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return ret;
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settings->d |= val;
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return 0;
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}
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static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll,
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struct clk_aic32x4_pll_muldiv *settings)
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{
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int ret;
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/* Change to use regmap_bulk_write for some if not all? */
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ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
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AIC32X4_PLL_R_MASK, settings->r);
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if (ret < 0)
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return ret;
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ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
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AIC32X4_PLL_P_MASK,
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settings->p << AIC32X4_PLL_P_SHIFT);
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if (ret < 0)
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return ret;
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ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j);
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if (ret < 0)
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return ret;
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ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8));
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if (ret < 0)
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return ret;
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ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff));
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if (ret < 0)
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return ret;
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return 0;
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}
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static unsigned long clk_aic32x4_pll_calc_rate(
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struct clk_aic32x4_pll_muldiv *settings,
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unsigned long parent_rate)
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{
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u64 rate;
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/*
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* We scale j by 10000 to account for the decimal part of P and divide
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* it back out later.
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*/
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rate = (u64) parent_rate * settings->r *
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((settings->j * 10000) + settings->d);
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return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000);
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}
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static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings,
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unsigned long rate, unsigned long parent_rate)
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{
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u64 multiplier;
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settings->p = parent_rate / AIC32X4_MAX_PLL_CLKIN + 1;
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if (settings->p > 8)
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return -1;
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/*
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* We scale this figure by 10000 so that we can get the decimal part
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* of the multiplier. This is because we can't do floating point
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* math in the kernel.
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*/
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multiplier = (u64) rate * settings->p * 10000;
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do_div(multiplier, parent_rate);
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/*
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* J can't be over 64, so R can scale this.
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* R can't be greater than 4.
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*/
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settings->r = ((u32) multiplier / 640000) + 1;
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if (settings->r > 4)
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return -1;
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do_div(multiplier, settings->r);
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/*
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* J can't be < 1.
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*/
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if (multiplier < 10000)
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return -1;
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/* Figure out the integer part, J, and the fractional part, D. */
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settings->j = (u32) multiplier / 10000;
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settings->d = (u32) multiplier % 10000;
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return 0;
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}
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static unsigned long clk_aic32x4_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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struct clk_aic32x4_pll_muldiv settings;
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int ret;
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ret = clk_aic32x4_pll_get_muldiv(pll, &settings);
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if (ret < 0)
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return 0;
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return clk_aic32x4_pll_calc_rate(&settings, parent_rate);
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}
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static long clk_aic32x4_pll_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_aic32x4_pll_muldiv settings;
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int ret;
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ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, *parent_rate);
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if (ret < 0)
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return 0;
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return clk_aic32x4_pll_calc_rate(&settings, *parent_rate);
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}
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static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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struct clk_aic32x4_pll_muldiv settings;
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int ret;
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ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, parent_rate);
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if (ret < 0)
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return -EINVAL;
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ret = clk_aic32x4_pll_set_muldiv(pll, &settings);
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if (ret)
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return ret;
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/* 10ms is the delay to wait before the clocks are stable */
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msleep(10);
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return 0;
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}
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static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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return regmap_update_bits(pll->regmap,
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AIC32X4_CLKMUX,
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AIC32X4_PLL_CLKIN_MASK,
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index << AIC32X4_PLL_CLKIN_SHIFT);
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}
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static u8 clk_aic32x4_pll_get_parent(struct clk_hw *hw)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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unsigned int val;
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regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
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return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT;
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}
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static const struct clk_ops aic32x4_pll_ops = {
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.prepare = clk_aic32x4_pll_prepare,
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.unprepare = clk_aic32x4_pll_unprepare,
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.is_prepared = clk_aic32x4_pll_is_prepared,
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.recalc_rate = clk_aic32x4_pll_recalc_rate,
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.round_rate = clk_aic32x4_pll_round_rate,
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.set_rate = clk_aic32x4_pll_set_rate,
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.set_parent = clk_aic32x4_pll_set_parent,
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.get_parent = clk_aic32x4_pll_get_parent,
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};
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static int clk_aic32x4_codec_clkin_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
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return regmap_update_bits(mux->regmap,
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AIC32X4_CLKMUX,
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AIC32X4_CODEC_CLKIN_MASK, index << AIC32X4_CODEC_CLKIN_SHIFT);
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}
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static u8 clk_aic32x4_codec_clkin_get_parent(struct clk_hw *hw)
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{
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struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
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unsigned int val;
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regmap_read(mux->regmap, AIC32X4_CLKMUX, &val);
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return (val & AIC32X4_CODEC_CLKIN_MASK) >> AIC32X4_CODEC_CLKIN_SHIFT;
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}
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static const struct clk_ops aic32x4_codec_clkin_ops = {
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.set_parent = clk_aic32x4_codec_clkin_set_parent,
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.get_parent = clk_aic32x4_codec_clkin_get_parent,
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};
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static int clk_aic32x4_div_prepare(struct clk_hw *hw)
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{
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struct clk_aic32x4 *div = to_clk_aic32x4(hw);
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return regmap_update_bits(div->regmap, div->reg,
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AIC32X4_DIVEN, AIC32X4_DIVEN);
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}
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static void clk_aic32x4_div_unprepare(struct clk_hw *hw)
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{
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struct clk_aic32x4 *div = to_clk_aic32x4(hw);
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regmap_update_bits(div->regmap, div->reg,
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AIC32X4_DIVEN, 0);
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}
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static int clk_aic32x4_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *div = to_clk_aic32x4(hw);
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u8 divisor;
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divisor = DIV_ROUND_UP(parent_rate, rate);
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if (divisor > 128)
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return -EINVAL;
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return regmap_update_bits(div->regmap, div->reg,
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AIC32X4_DIV_MASK, divisor);
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}
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static long clk_aic32x4_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned long divisor;
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divisor = DIV_ROUND_UP(*parent_rate, rate);
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if (divisor > 128)
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return -EINVAL;
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return DIV_ROUND_UP(*parent_rate, divisor);
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}
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static unsigned long clk_aic32x4_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *div = to_clk_aic32x4(hw);
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unsigned int val;
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regmap_read(div->regmap, div->reg, &val);
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return DIV_ROUND_UP(parent_rate, val & AIC32X4_DIV_MASK);
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}
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static const struct clk_ops aic32x4_div_ops = {
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.prepare = clk_aic32x4_div_prepare,
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.unprepare = clk_aic32x4_div_unprepare,
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.set_rate = clk_aic32x4_div_set_rate,
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.round_rate = clk_aic32x4_div_round_rate,
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.recalc_rate = clk_aic32x4_div_recalc_rate,
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};
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static int clk_aic32x4_bdiv_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
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return regmap_update_bits(mux->regmap, AIC32X4_IFACE3,
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AIC32X4_BDIVCLK_MASK, index);
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}
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static u8 clk_aic32x4_bdiv_get_parent(struct clk_hw *hw)
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{
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struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
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unsigned int val;
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regmap_read(mux->regmap, AIC32X4_IFACE3, &val);
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return val & AIC32X4_BDIVCLK_MASK;
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}
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static const struct clk_ops aic32x4_bdiv_ops = {
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.prepare = clk_aic32x4_div_prepare,
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.unprepare = clk_aic32x4_div_unprepare,
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.set_parent = clk_aic32x4_bdiv_set_parent,
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.get_parent = clk_aic32x4_bdiv_get_parent,
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.set_rate = clk_aic32x4_div_set_rate,
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.round_rate = clk_aic32x4_div_round_rate,
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.recalc_rate = clk_aic32x4_div_recalc_rate,
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};
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static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
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{
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.name = "pll",
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.parent_names =
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(const char* []) { "mclk", "bclk", "gpio", "din" },
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.num_parents = 4,
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.ops = &aic32x4_pll_ops,
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.reg = 0,
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},
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{
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.name = "codec_clkin",
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.parent_names =
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(const char *[]) { "mclk", "bclk", "gpio", "pll" },
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.num_parents = 4,
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.ops = &aic32x4_codec_clkin_ops,
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.reg = 0,
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},
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{
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.name = "ndac",
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.parent_names = (const char * []) { "codec_clkin" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_NDAC,
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},
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{
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.name = "mdac",
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.parent_names = (const char * []) { "ndac" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_MDAC,
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},
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{
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.name = "nadc",
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.parent_names = (const char * []) { "codec_clkin" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_NADC,
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},
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{
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.name = "madc",
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.parent_names = (const char * []) { "nadc" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_MADC,
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},
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{
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.name = "bdiv",
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.parent_names =
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(const char *[]) { "ndac", "mdac", "nadc", "madc" },
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.num_parents = 4,
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.ops = &aic32x4_bdiv_ops,
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.reg = AIC32X4_BCLKN,
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},
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};
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static struct clk *aic32x4_register_clk(struct device *dev,
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struct aic32x4_clkdesc *desc)
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{
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struct clk_init_data init;
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struct clk_aic32x4 *priv;
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const char *devname = dev_name(dev);
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init.ops = desc->ops;
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init.name = desc->name;
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init.parent_names = desc->parent_names;
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init.num_parents = desc->num_parents;
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init.flags = 0;
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priv = devm_kzalloc(dev, sizeof(struct clk_aic32x4), GFP_KERNEL);
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if (priv == NULL)
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return (struct clk *) -ENOMEM;
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priv->dev = dev;
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priv->hw.init = &init;
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priv->regmap = dev_get_regmap(dev, NULL);
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priv->reg = desc->reg;
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clk_hw_register_clkdev(&priv->hw, desc->name, devname);
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return devm_clk_register(dev, &priv->hw);
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}
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int aic32x4_register_clocks(struct device *dev, const char *mclk_name)
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{
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int i;
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/*
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* These lines are here to preserve the current functionality of
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* the driver with regard to the DT. These should eventually be set
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* by DT nodes so that the connections can be set up in configuration
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* rather than code.
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*/
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aic32x4_clkdesc_array[0].parent_names =
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(const char* []) { mclk_name, "bclk", "gpio", "din" };
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aic32x4_clkdesc_array[1].parent_names =
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(const char *[]) { mclk_name, "bclk", "gpio", "pll" };
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for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i)
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aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]);
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return 0;
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}
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EXPORT_SYMBOL_GPL(aic32x4_register_clocks);
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