750 lines
18 KiB
C
750 lines
18 KiB
C
/*
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* ALSA SoC Synopsys I2S Audio Layer
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*
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* sound/soc/dwc/designware_i2s.c
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*
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* Copyright (C) 2010 ST Microelectronics
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* Rajeev Kumar <rajeevkumar.linux@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <sound/designware_i2s.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/dmaengine_pcm.h>
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#include "local.h"
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static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
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{
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writel(val, io_base + reg);
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}
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static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
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{
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return readl(io_base + reg);
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}
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static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
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{
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u32 i = 0;
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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for (i = 0; i < 4; i++)
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i2s_write_reg(dev->i2s_base, TER(i), 0);
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} else {
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for (i = 0; i < 4; i++)
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i2s_write_reg(dev->i2s_base, RER(i), 0);
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}
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}
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static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
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{
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u32 i = 0;
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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for (i = 0; i < 4; i++)
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i2s_read_reg(dev->i2s_base, TOR(i));
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} else {
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for (i = 0; i < 4; i++)
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i2s_read_reg(dev->i2s_base, ROR(i));
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}
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}
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static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
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int chan_nr)
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{
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u32 i, irq;
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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for (i = 0; i < (chan_nr / 2); i++) {
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irq = i2s_read_reg(dev->i2s_base, IMR(i));
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i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
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}
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} else {
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for (i = 0; i < (chan_nr / 2); i++) {
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irq = i2s_read_reg(dev->i2s_base, IMR(i));
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i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
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}
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}
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}
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static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
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int chan_nr)
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{
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u32 i, irq;
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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for (i = 0; i < (chan_nr / 2); i++) {
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irq = i2s_read_reg(dev->i2s_base, IMR(i));
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i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
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}
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} else {
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for (i = 0; i < (chan_nr / 2); i++) {
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irq = i2s_read_reg(dev->i2s_base, IMR(i));
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i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
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}
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}
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}
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static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
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{
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struct dw_i2s_dev *dev = dev_id;
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bool irq_valid = false;
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u32 isr[4];
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int i;
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for (i = 0; i < 4; i++)
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isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
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i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
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i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
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for (i = 0; i < 4; i++) {
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/*
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* Check if TX fifo is empty. If empty fill FIFO with samples
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* NOTE: Only two channels supported
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*/
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if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
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dw_pcm_push_tx(dev);
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irq_valid = true;
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}
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/*
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* Data available. Retrieve samples from FIFO
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* NOTE: Only two channels supported
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*/
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if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
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dw_pcm_pop_rx(dev);
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irq_valid = true;
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}
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/* Error Handling: TX */
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if (isr[i] & ISR_TXFO) {
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dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i);
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irq_valid = true;
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}
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/* Error Handling: TX */
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if (isr[i] & ISR_RXFO) {
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dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i);
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irq_valid = true;
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}
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}
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if (irq_valid)
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return IRQ_HANDLED;
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else
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return IRQ_NONE;
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}
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static void i2s_start(struct dw_i2s_dev *dev,
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struct snd_pcm_substream *substream)
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{
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struct i2s_clk_config_data *config = &dev->config;
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i2s_write_reg(dev->i2s_base, IER, 1);
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i2s_enable_irqs(dev, substream->stream, config->chan_nr);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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i2s_write_reg(dev->i2s_base, ITER, 1);
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else
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i2s_write_reg(dev->i2s_base, IRER, 1);
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i2s_write_reg(dev->i2s_base, CER, 1);
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}
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static void i2s_stop(struct dw_i2s_dev *dev,
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struct snd_pcm_substream *substream)
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{
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i2s_clear_irqs(dev, substream->stream);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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i2s_write_reg(dev->i2s_base, ITER, 0);
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else
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i2s_write_reg(dev->i2s_base, IRER, 0);
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i2s_disable_irqs(dev, substream->stream, 8);
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if (!dev->active) {
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i2s_write_reg(dev->i2s_base, CER, 0);
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i2s_write_reg(dev->i2s_base, IER, 0);
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}
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}
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static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
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{
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u32 ch_reg;
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struct i2s_clk_config_data *config = &dev->config;
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i2s_disable_channels(dev, stream);
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for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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i2s_write_reg(dev->i2s_base, TCR(ch_reg),
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dev->xfer_resolution);
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i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
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dev->fifo_th - 1);
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i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
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} else {
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i2s_write_reg(dev->i2s_base, RCR(ch_reg),
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dev->xfer_resolution);
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i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
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dev->fifo_th - 1);
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i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
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}
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}
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}
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static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
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{
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struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
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struct i2s_clk_config_data *config = &dev->config;
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int ret;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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config->data_width = 16;
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dev->ccr = 0x00;
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dev->xfer_resolution = 0x02;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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config->data_width = 24;
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dev->ccr = 0x08;
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dev->xfer_resolution = 0x04;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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config->data_width = 32;
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dev->ccr = 0x10;
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dev->xfer_resolution = 0x05;
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break;
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default:
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dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
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return -EINVAL;
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}
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config->chan_nr = params_channels(params);
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switch (config->chan_nr) {
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case EIGHT_CHANNEL_SUPPORT:
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case SIX_CHANNEL_SUPPORT:
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case FOUR_CHANNEL_SUPPORT:
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case TWO_CHANNEL_SUPPORT:
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break;
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default:
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dev_err(dev->dev, "channel not supported\n");
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return -EINVAL;
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}
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dw_i2s_config(dev, substream->stream);
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i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
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config->sample_rate = params_rate(params);
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if (dev->capability & DW_I2S_MASTER) {
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if (dev->i2s_clk_cfg) {
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ret = dev->i2s_clk_cfg(config);
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if (ret < 0) {
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dev_err(dev->dev, "runtime audio clk config fail\n");
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return ret;
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}
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} else {
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u32 bitclk = config->sample_rate *
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config->data_width * 2;
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ret = clk_set_rate(dev->clk, bitclk);
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if (ret) {
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dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
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ret);
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return ret;
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}
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}
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}
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return 0;
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}
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static int dw_i2s_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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i2s_write_reg(dev->i2s_base, TXFFR, 1);
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else
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i2s_write_reg(dev->i2s_base, RXFFR, 1);
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return 0;
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}
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static int dw_i2s_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
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int ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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dev->active++;
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i2s_start(dev, substream);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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dev->active--;
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i2s_stop(dev, substream);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
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int ret = 0;
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switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
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case SND_SOC_DAIFMT_BC_FC:
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if (dev->capability & DW_I2S_SLAVE)
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ret = 0;
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else
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ret = -EINVAL;
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break;
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case SND_SOC_DAIFMT_BP_FP:
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if (dev->capability & DW_I2S_MASTER)
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ret = 0;
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else
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ret = -EINVAL;
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break;
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case SND_SOC_DAIFMT_BC_FP:
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case SND_SOC_DAIFMT_BP_FC:
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ret = -EINVAL;
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break;
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default:
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dev_dbg(dev->dev, "dwc : Invalid clock provider format\n");
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
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.hw_params = dw_i2s_hw_params,
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.prepare = dw_i2s_prepare,
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.trigger = dw_i2s_trigger,
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.set_fmt = dw_i2s_set_fmt,
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};
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#ifdef CONFIG_PM
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static int dw_i2s_runtime_suspend(struct device *dev)
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{
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struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
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if (dw_dev->capability & DW_I2S_MASTER)
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clk_disable(dw_dev->clk);
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return 0;
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}
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static int dw_i2s_runtime_resume(struct device *dev)
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{
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struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
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int ret;
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if (dw_dev->capability & DW_I2S_MASTER) {
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ret = clk_enable(dw_dev->clk);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int dw_i2s_suspend(struct snd_soc_component *component)
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{
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struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
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if (dev->capability & DW_I2S_MASTER)
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clk_disable(dev->clk);
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return 0;
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}
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static int dw_i2s_resume(struct snd_soc_component *component)
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{
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struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
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struct snd_soc_dai *dai;
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int stream, ret;
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if (dev->capability & DW_I2S_MASTER) {
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ret = clk_enable(dev->clk);
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if (ret)
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return ret;
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}
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for_each_component_dais(component, dai) {
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for_each_pcm_streams(stream)
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if (snd_soc_dai_stream_active(dai, stream))
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dw_i2s_config(dev, stream);
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}
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return 0;
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}
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#else
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#define dw_i2s_suspend NULL
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#define dw_i2s_resume NULL
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#endif
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static const struct snd_soc_component_driver dw_i2s_component = {
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.name = "dw-i2s",
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.suspend = dw_i2s_suspend,
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.resume = dw_i2s_resume,
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.legacy_dai_naming = 1,
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};
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/*
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* The following tables allow a direct lookup of various parameters
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* defined in the I2S block's configuration in terms of sound system
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* parameters. Each table is sized to the number of entries possible
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* according to the number of configuration bits describing an I2S
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* block parameter.
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*/
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/* Maximum bit resolution of a channel - not uniformly spaced */
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static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
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12, 16, 20, 24, 32, 0, 0, 0
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};
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/* Width of (DMA) bus */
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static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
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DMA_SLAVE_BUSWIDTH_1_BYTE,
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DMA_SLAVE_BUSWIDTH_2_BYTES,
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DMA_SLAVE_BUSWIDTH_4_BYTES,
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DMA_SLAVE_BUSWIDTH_UNDEFINED
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};
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/* PCM format to support channel resolution */
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static const u32 formats[COMP_MAX_WORDSIZE] = {
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SNDRV_PCM_FMTBIT_S16_LE,
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SNDRV_PCM_FMTBIT_S16_LE,
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SNDRV_PCM_FMTBIT_S24_LE,
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SNDRV_PCM_FMTBIT_S24_LE,
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SNDRV_PCM_FMTBIT_S32_LE,
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0,
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0,
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0
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};
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static int dw_configure_dai(struct dw_i2s_dev *dev,
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struct snd_soc_dai_driver *dw_i2s_dai,
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unsigned int rates)
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{
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/*
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* Read component parameter registers to extract
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* the I2S block's configuration.
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*/
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u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
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u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
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u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
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u32 idx;
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if (dev->capability & DWC_I2S_RECORD &&
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dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
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comp1 = comp1 & ~BIT(5);
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if (dev->capability & DWC_I2S_PLAY &&
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dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
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comp1 = comp1 & ~BIT(6);
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if (COMP1_TX_ENABLED(comp1)) {
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dev_dbg(dev->dev, " designware: play supported\n");
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idx = COMP1_TX_WORDSIZE_0(comp1);
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if (WARN_ON(idx >= ARRAY_SIZE(formats)))
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return -EINVAL;
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if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
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idx = 1;
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dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
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dw_i2s_dai->playback.channels_max =
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1 << (COMP1_TX_CHANNELS(comp1) + 1);
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dw_i2s_dai->playback.formats = formats[idx];
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dw_i2s_dai->playback.rates = rates;
|
|
}
|
|
|
|
if (COMP1_RX_ENABLED(comp1)) {
|
|
dev_dbg(dev->dev, "designware: record supported\n");
|
|
idx = COMP2_RX_WORDSIZE_0(comp2);
|
|
if (WARN_ON(idx >= ARRAY_SIZE(formats)))
|
|
return -EINVAL;
|
|
if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
|
|
idx = 1;
|
|
dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
|
|
dw_i2s_dai->capture.channels_max =
|
|
1 << (COMP1_RX_CHANNELS(comp1) + 1);
|
|
dw_i2s_dai->capture.formats = formats[idx];
|
|
dw_i2s_dai->capture.rates = rates;
|
|
}
|
|
|
|
if (COMP1_MODE_EN(comp1)) {
|
|
dev_dbg(dev->dev, "designware: i2s master mode supported\n");
|
|
dev->capability |= DW_I2S_MASTER;
|
|
} else {
|
|
dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
|
|
dev->capability |= DW_I2S_SLAVE;
|
|
}
|
|
|
|
dev->fifo_th = fifo_depth / 2;
|
|
return 0;
|
|
}
|
|
|
|
static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
|
|
struct snd_soc_dai_driver *dw_i2s_dai,
|
|
struct resource *res,
|
|
const struct i2s_platform_data *pdata)
|
|
{
|
|
u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
|
|
u32 idx = COMP1_APB_DATA_WIDTH(comp1);
|
|
int ret;
|
|
|
|
if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
|
|
return -EINVAL;
|
|
|
|
ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
|
|
idx = 1;
|
|
/* Set DMA slaves info */
|
|
dev->play_dma_data.pd.data = pdata->play_dma_data;
|
|
dev->capture_dma_data.pd.data = pdata->capture_dma_data;
|
|
dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
|
|
dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
|
|
dev->play_dma_data.pd.max_burst = 16;
|
|
dev->capture_dma_data.pd.max_burst = 16;
|
|
dev->play_dma_data.pd.addr_width = bus_widths[idx];
|
|
dev->capture_dma_data.pd.addr_width = bus_widths[idx];
|
|
dev->play_dma_data.pd.filter = pdata->filter;
|
|
dev->capture_dma_data.pd.filter = pdata->filter;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
|
|
struct snd_soc_dai_driver *dw_i2s_dai,
|
|
struct resource *res)
|
|
{
|
|
u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
|
|
u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
|
|
u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
|
|
u32 idx = COMP1_APB_DATA_WIDTH(comp1);
|
|
u32 idx2;
|
|
int ret;
|
|
|
|
if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
|
|
return -EINVAL;
|
|
|
|
ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (COMP1_TX_ENABLED(comp1)) {
|
|
idx2 = COMP1_TX_WORDSIZE_0(comp1);
|
|
|
|
dev->capability |= DWC_I2S_PLAY;
|
|
dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
|
|
dev->play_dma_data.dt.addr_width = bus_widths[idx];
|
|
dev->play_dma_data.dt.fifo_size = fifo_depth *
|
|
(fifo_width[idx2]) >> 8;
|
|
dev->play_dma_data.dt.maxburst = 16;
|
|
}
|
|
if (COMP1_RX_ENABLED(comp1)) {
|
|
idx2 = COMP2_RX_WORDSIZE_0(comp2);
|
|
|
|
dev->capability |= DWC_I2S_RECORD;
|
|
dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
|
|
dev->capture_dma_data.dt.addr_width = bus_widths[idx];
|
|
dev->capture_dma_data.dt.fifo_size = fifo_depth *
|
|
(fifo_width[idx2] >> 8);
|
|
dev->capture_dma_data.dt.maxburst = 16;
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static int dw_i2s_dai_probe(struct snd_soc_dai *dai)
|
|
{
|
|
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
|
|
|
|
snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
|
|
return 0;
|
|
}
|
|
|
|
static int dw_i2s_probe(struct platform_device *pdev)
|
|
{
|
|
const struct i2s_platform_data *pdata = pdev->dev.platform_data;
|
|
struct dw_i2s_dev *dev;
|
|
struct resource *res;
|
|
int ret, irq;
|
|
struct snd_soc_dai_driver *dw_i2s_dai;
|
|
const char *clk_id;
|
|
|
|
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
|
|
dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
|
|
if (!dw_i2s_dai)
|
|
return -ENOMEM;
|
|
|
|
dw_i2s_dai->ops = &dw_i2s_dai_ops;
|
|
dw_i2s_dai->probe = dw_i2s_dai_probe;
|
|
|
|
dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
|
if (IS_ERR(dev->i2s_base))
|
|
return PTR_ERR(dev->i2s_base);
|
|
|
|
dev->dev = &pdev->dev;
|
|
|
|
irq = platform_get_irq_optional(pdev, 0);
|
|
if (irq >= 0) {
|
|
ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
|
|
pdev->name, dev);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to request irq\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
|
|
dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
|
|
if (pdata) {
|
|
dev->capability = pdata->cap;
|
|
clk_id = NULL;
|
|
dev->quirks = pdata->quirks;
|
|
if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
|
|
dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
|
|
dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
|
|
}
|
|
ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
|
|
} else {
|
|
clk_id = "i2sclk";
|
|
ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
|
|
}
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (dev->capability & DW_I2S_MASTER) {
|
|
if (pdata) {
|
|
dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
|
|
if (!dev->i2s_clk_cfg) {
|
|
dev_err(&pdev->dev, "no clock configure method\n");
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
dev->clk = devm_clk_get(&pdev->dev, clk_id);
|
|
|
|
if (IS_ERR(dev->clk))
|
|
return PTR_ERR(dev->clk);
|
|
|
|
ret = clk_prepare_enable(dev->clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
dev_set_drvdata(&pdev->dev, dev);
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
|
|
dw_i2s_dai, 1);
|
|
if (ret != 0) {
|
|
dev_err(&pdev->dev, "not able to register dai\n");
|
|
goto err_clk_disable;
|
|
}
|
|
|
|
if (!pdata) {
|
|
if (irq >= 0) {
|
|
ret = dw_pcm_register(pdev);
|
|
dev->use_pio = true;
|
|
} else {
|
|
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
|
|
0);
|
|
dev->use_pio = false;
|
|
}
|
|
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "could not register pcm: %d\n",
|
|
ret);
|
|
goto err_clk_disable;
|
|
}
|
|
}
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
return 0;
|
|
|
|
err_clk_disable:
|
|
if (dev->capability & DW_I2S_MASTER)
|
|
clk_disable_unprepare(dev->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int dw_i2s_remove(struct platform_device *pdev)
|
|
{
|
|
struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
|
|
|
|
if (dev->capability & DW_I2S_MASTER)
|
|
clk_disable_unprepare(dev->clk);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id dw_i2s_of_match[] = {
|
|
{ .compatible = "snps,designware-i2s", },
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
|
|
#endif
|
|
|
|
static const struct dev_pm_ops dwc_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver dw_i2s_driver = {
|
|
.probe = dw_i2s_probe,
|
|
.remove = dw_i2s_remove,
|
|
.driver = {
|
|
.name = "designware-i2s",
|
|
.of_match_table = of_match_ptr(dw_i2s_of_match),
|
|
.pm = &dwc_pm_ops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(dw_i2s_driver);
|
|
|
|
MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
|
|
MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:designware_i2s");
|