412 lines
12 KiB
C
412 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved.
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*
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* lpass.h - Definitions for the QTi LPASS
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*/
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#ifndef __LPASS_H__
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#define __LPASS_H__
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#include <linux/clk.h>
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#include <linux/compiler.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/sound/qcom,lpass.h>
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#include "lpass-hdmi.h"
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#define LPASS_AHBIX_CLOCK_FREQUENCY 131072000
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#define LPASS_MAX_PORTS (LPASS_CDC_DMA_VA_TX8 + 1)
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#define LPASS_MAX_MI2S_PORTS (8)
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#define LPASS_MAX_DMA_CHANNELS (8)
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#define LPASS_MAX_HDMI_DMA_CHANNELS (4)
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#define LPASS_MAX_CDC_DMA_CHANNELS (8)
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#define LPASS_MAX_VA_CDC_DMA_CHANNELS (8)
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#define LPASS_CDC_DMA_INTF_ONE_CHANNEL (0x01)
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#define LPASS_CDC_DMA_INTF_TWO_CHANNEL (0x03)
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#define LPASS_CDC_DMA_INTF_FOUR_CHANNEL (0x0F)
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#define LPASS_CDC_DMA_INTF_SIX_CHANNEL (0x3F)
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#define LPASS_CDC_DMA_INTF_EIGHT_CHANNEL (0xFF)
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#define LPASS_ACTIVE_PDS (4)
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#define LPASS_PROXY_PDS (8)
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#define QCOM_REGMAP_FIELD_ALLOC(d, m, f, mf) \
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do { \
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mf = devm_regmap_field_alloc(d, m, f); \
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if (IS_ERR(mf)) \
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return -EINVAL; \
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} while (0)
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static inline bool is_cdc_dma_port(int dai_id)
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{
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switch (dai_id) {
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case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
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case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
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case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
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return true;
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}
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return false;
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}
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static inline bool is_rxtx_cdc_dma_port(int dai_id)
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{
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switch (dai_id) {
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case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
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case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
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return true;
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}
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return false;
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}
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struct lpaif_i2sctl {
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struct regmap_field *loopback;
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struct regmap_field *spken;
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struct regmap_field *spkmode;
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struct regmap_field *spkmono;
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struct regmap_field *micen;
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struct regmap_field *micmode;
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struct regmap_field *micmono;
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struct regmap_field *wssrc;
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struct regmap_field *bitwidth;
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};
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struct lpaif_dmactl {
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struct regmap_field *intf;
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struct regmap_field *bursten;
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struct regmap_field *wpscnt;
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struct regmap_field *fifowm;
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struct regmap_field *enable;
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struct regmap_field *dyncclk;
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struct regmap_field *burst8;
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struct regmap_field *burst16;
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struct regmap_field *dynburst;
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struct regmap_field *codec_enable;
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struct regmap_field *codec_pack;
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struct regmap_field *codec_intf;
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struct regmap_field *codec_fs_sel;
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struct regmap_field *codec_channel;
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struct regmap_field *codec_fs_delay;
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};
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/* Both the CPU DAI and platform drivers will access this data */
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struct lpass_data {
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/* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
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struct clk *ahbix_clk;
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/* MI2S system clock */
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struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS];
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/* MI2S bit clock (derived from system clock by a divider */
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struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS];
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struct clk *codec_mem0;
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struct clk *codec_mem1;
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struct clk *codec_mem2;
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struct clk *va_mem0;
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/* MI2S SD lines to use for playback/capture */
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unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS];
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unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS];
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/* The state of MI2S prepare dai_ops was called */
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bool mi2s_was_prepared[LPASS_MAX_MI2S_PORTS];
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int hdmi_port_enable;
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int codec_dma_enable;
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/* low-power audio interface (LPAIF) registers */
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void __iomem *lpaif;
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void __iomem *hdmiif;
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void __iomem *rxtx_lpaif;
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void __iomem *va_lpaif;
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u32 rxtx_cdc_dma_lpm_buf;
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u32 va_cdc_dma_lpm_buf;
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/* regmap backed by the low-power audio interface (LPAIF) registers */
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struct regmap *lpaif_map;
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struct regmap *hdmiif_map;
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struct regmap *rxtx_lpaif_map;
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struct regmap *va_lpaif_map;
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/* interrupts from the low-power audio interface (LPAIF) */
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int lpaif_irq;
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int hdmiif_irq;
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int rxtxif_irq;
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int vaif_irq;
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/* SOC specific variations in the LPASS IP integration */
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struct lpass_variant *variant;
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/* bit map to keep track of static channel allocations */
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unsigned long dma_ch_bit_map;
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unsigned long hdmi_dma_ch_bit_map;
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unsigned long rxtx_dma_ch_bit_map;
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unsigned long va_dma_ch_bit_map;
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/* used it for handling interrupt per dma channel */
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struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS];
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struct snd_pcm_substream *hdmi_substream[LPASS_MAX_HDMI_DMA_CHANNELS];
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struct snd_pcm_substream *rxtx_substream[LPASS_MAX_CDC_DMA_CHANNELS];
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struct snd_pcm_substream *va_substream[LPASS_MAX_CDC_DMA_CHANNELS];
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/* SOC specific clock list */
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struct clk_bulk_data *clks;
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int num_clks;
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/* Regmap fields of I2SCTL & DMACTL registers bitfields */
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struct lpaif_i2sctl *i2sctl;
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struct lpaif_dmactl *rd_dmactl;
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struct lpaif_dmactl *wr_dmactl;
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struct lpaif_dmactl *hdmi_rd_dmactl;
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/* Regmap fields of CODEC DMA CTRL registers */
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struct lpaif_dmactl *rxtx_rd_dmactl;
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struct lpaif_dmactl *rxtx_wr_dmactl;
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struct lpaif_dmactl *va_wr_dmactl;
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/* Regmap fields of HDMI_CTRL registers*/
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struct regmap_field *hdmitx_legacy_en;
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struct regmap_field *hdmitx_parity_calc_en;
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struct regmap_field *hdmitx_ch_msb[LPASS_MAX_HDMI_DMA_CHANNELS];
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struct regmap_field *hdmitx_ch_lsb[LPASS_MAX_HDMI_DMA_CHANNELS];
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struct lpass_hdmi_tx_ctl *tx_ctl;
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struct lpass_vbit_ctrl *vbit_ctl;
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struct lpass_hdmitx_dmactl *hdmi_tx_dmactl[LPASS_MAX_HDMI_DMA_CHANNELS];
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struct lpass_dp_metadata_ctl *meta_ctl;
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struct lpass_sstream_ctl *sstream_ctl;
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};
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/* Vairant data per each SOC */
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struct lpass_variant {
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u32 irq_reg_base;
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u32 irq_reg_stride;
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u32 irq_ports;
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u32 rdma_reg_base;
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u32 rdma_reg_stride;
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u32 rdma_channels;
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u32 hdmi_rdma_reg_base;
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u32 hdmi_rdma_reg_stride;
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u32 hdmi_rdma_channels;
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u32 wrdma_reg_base;
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u32 wrdma_reg_stride;
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u32 wrdma_channels;
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u32 rxtx_irq_reg_base;
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u32 rxtx_irq_reg_stride;
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u32 rxtx_irq_ports;
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u32 rxtx_rdma_reg_base;
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u32 rxtx_rdma_reg_stride;
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u32 rxtx_rdma_channels;
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u32 rxtx_wrdma_reg_base;
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u32 rxtx_wrdma_reg_stride;
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u32 rxtx_wrdma_channels;
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u32 va_irq_reg_base;
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u32 va_irq_reg_stride;
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u32 va_irq_ports;
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u32 va_rdma_reg_base;
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u32 va_rdma_reg_stride;
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u32 va_rdma_channels;
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u32 va_wrdma_reg_base;
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u32 va_wrdma_reg_stride;
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u32 va_wrdma_channels;
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u32 i2sctrl_reg_base;
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u32 i2sctrl_reg_stride;
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u32 i2s_ports;
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/* I2SCTL Register fields */
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struct reg_field loopback;
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struct reg_field spken;
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struct reg_field spkmode;
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struct reg_field spkmono;
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struct reg_field micen;
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struct reg_field micmode;
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struct reg_field micmono;
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struct reg_field wssrc;
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struct reg_field bitwidth;
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u32 hdmi_irq_reg_base;
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u32 hdmi_irq_reg_stride;
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u32 hdmi_irq_ports;
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/* HDMI specific controls */
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u32 hdmi_tx_ctl_addr;
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u32 hdmi_legacy_addr;
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u32 hdmi_vbit_addr;
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u32 hdmi_ch_lsb_addr;
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u32 hdmi_ch_msb_addr;
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u32 ch_stride;
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u32 hdmi_parity_addr;
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u32 hdmi_dmactl_addr;
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u32 hdmi_dma_stride;
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u32 hdmi_DP_addr;
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u32 hdmi_sstream_addr;
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/* HDMI SSTREAM CTRL fields */
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struct reg_field sstream_en;
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struct reg_field dma_sel;
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struct reg_field auto_bbit_en;
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struct reg_field layout;
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struct reg_field layout_sp;
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struct reg_field set_sp_on_en;
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struct reg_field dp_audio;
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struct reg_field dp_staffing_en;
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struct reg_field dp_sp_b_hw_en;
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/* HDMI DP METADATA CTL fields */
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struct reg_field mute;
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struct reg_field as_sdp_cc;
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struct reg_field as_sdp_ct;
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struct reg_field aif_db4;
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struct reg_field frequency;
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struct reg_field mst_index;
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struct reg_field dptx_index;
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/* HDMI TX CTRL fields */
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struct reg_field soft_reset;
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struct reg_field force_reset;
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/* HDMI TX DMA CTRL */
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struct reg_field use_hw_chs;
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struct reg_field use_hw_usr;
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struct reg_field hw_chs_sel;
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struct reg_field hw_usr_sel;
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/* HDMI VBIT CTRL */
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struct reg_field replace_vbit;
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struct reg_field vbit_stream;
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/* HDMI TX LEGACY */
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struct reg_field legacy_en;
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/* HDMI TX PARITY */
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struct reg_field calc_en;
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/* HDMI CH LSB */
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struct reg_field lsb_bits;
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/* HDMI CH MSB */
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struct reg_field msb_bits;
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struct reg_field hdmi_rdma_bursten;
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struct reg_field hdmi_rdma_wpscnt;
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struct reg_field hdmi_rdma_fifowm;
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struct reg_field hdmi_rdma_enable;
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struct reg_field hdmi_rdma_dyncclk;
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struct reg_field hdmi_rdma_burst8;
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struct reg_field hdmi_rdma_burst16;
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struct reg_field hdmi_rdma_dynburst;
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/* RD_DMA Register fields */
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struct reg_field rdma_intf;
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struct reg_field rdma_bursten;
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struct reg_field rdma_wpscnt;
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struct reg_field rdma_fifowm;
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struct reg_field rdma_enable;
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struct reg_field rdma_dyncclk;
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/* WR_DMA Register fields */
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struct reg_field wrdma_intf;
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struct reg_field wrdma_bursten;
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struct reg_field wrdma_wpscnt;
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struct reg_field wrdma_fifowm;
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struct reg_field wrdma_enable;
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struct reg_field wrdma_dyncclk;
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/* CDC RXTX RD_DMA */
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struct reg_field rxtx_rdma_intf;
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struct reg_field rxtx_rdma_bursten;
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struct reg_field rxtx_rdma_wpscnt;
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struct reg_field rxtx_rdma_fifowm;
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struct reg_field rxtx_rdma_enable;
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struct reg_field rxtx_rdma_dyncclk;
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struct reg_field rxtx_rdma_burst8;
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struct reg_field rxtx_rdma_burst16;
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struct reg_field rxtx_rdma_dynburst;
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struct reg_field rxtx_rdma_codec_enable;
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struct reg_field rxtx_rdma_codec_pack;
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struct reg_field rxtx_rdma_codec_intf;
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struct reg_field rxtx_rdma_codec_fs_sel;
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struct reg_field rxtx_rdma_codec_ch;
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struct reg_field rxtx_rdma_codec_fs_delay;
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/* CDC RXTX WR_DMA */
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struct reg_field rxtx_wrdma_intf;
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struct reg_field rxtx_wrdma_bursten;
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struct reg_field rxtx_wrdma_wpscnt;
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struct reg_field rxtx_wrdma_fifowm;
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struct reg_field rxtx_wrdma_enable;
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struct reg_field rxtx_wrdma_dyncclk;
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struct reg_field rxtx_wrdma_burst8;
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struct reg_field rxtx_wrdma_burst16;
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struct reg_field rxtx_wrdma_dynburst;
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struct reg_field rxtx_wrdma_codec_enable;
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struct reg_field rxtx_wrdma_codec_pack;
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struct reg_field rxtx_wrdma_codec_intf;
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struct reg_field rxtx_wrdma_codec_fs_sel;
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struct reg_field rxtx_wrdma_codec_ch;
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struct reg_field rxtx_wrdma_codec_fs_delay;
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/* CDC VA WR_DMA */
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struct reg_field va_wrdma_intf;
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struct reg_field va_wrdma_bursten;
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struct reg_field va_wrdma_wpscnt;
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struct reg_field va_wrdma_fifowm;
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struct reg_field va_wrdma_enable;
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struct reg_field va_wrdma_dyncclk;
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struct reg_field va_wrdma_burst8;
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struct reg_field va_wrdma_burst16;
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struct reg_field va_wrdma_dynburst;
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struct reg_field va_wrdma_codec_enable;
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struct reg_field va_wrdma_codec_pack;
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struct reg_field va_wrdma_codec_intf;
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struct reg_field va_wrdma_codec_fs_sel;
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struct reg_field va_wrdma_codec_ch;
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struct reg_field va_wrdma_codec_fs_delay;
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/**
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* on SOCs like APQ8016 the channel control bits start
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* at different offset to ipq806x
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**/
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u32 dmactl_audif_start;
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u32 wrdma_channel_start;
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u32 rxtx_wrdma_channel_start;
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u32 va_wrdma_channel_start;
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/* SOC specific initialization like clocks */
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int (*init)(struct platform_device *pdev);
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int (*exit)(struct platform_device *pdev);
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int (*alloc_dma_channel)(struct lpass_data *data, int direction, unsigned int dai_id);
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int (*free_dma_channel)(struct lpass_data *data, int ch, unsigned int dai_id);
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/* SOC specific dais */
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struct snd_soc_dai_driver *dai_driver;
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int num_dai;
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const char * const *dai_osr_clk_names;
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const char * const *dai_bit_clk_names;
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/* SOC specific clocks configuration */
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const char **clk_name;
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int num_clks;
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};
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struct lpass_pcm_data {
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int dma_ch;
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int i2s_port;
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};
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/* register the platform driver from the CPU DAI driver */
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int asoc_qcom_lpass_platform_register(struct platform_device *);
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int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev);
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void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev);
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int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev);
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int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai);
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extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops;
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int lpass_cpu_pcm_new(struct snd_soc_pcm_runtime *rtd,
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struct snd_soc_dai *dai);
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extern const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops;
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#endif /* __LPASS_H__ */
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