670 lines
16 KiB
C
670 lines
16 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright(c) 2022 Mediatek Inc. All rights reserved.
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//
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// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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// Tinghan Shen <tinghan.shen@mediatek.com>
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/*
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* Hardware interface for audio DSP on mt8186
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*/
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/module.h>
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#include <sound/sof.h>
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#include <sound/sof/xtensa.h>
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#include "../../ops.h"
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#include "../../sof-of-dev.h"
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#include "../../sof-audio.h"
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#include "../adsp_helper.h"
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#include "mt8186.h"
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#include "mt8186-clk.h"
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static int mt8186_get_mailbox_offset(struct snd_sof_dev *sdev)
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{
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return MBOX_OFFSET;
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}
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static int mt8186_get_window_offset(struct snd_sof_dev *sdev, u32 id)
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{
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return MBOX_OFFSET;
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}
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static int mt8186_send_msg(struct snd_sof_dev *sdev,
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struct snd_sof_ipc_msg *msg)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ);
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}
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static void mt8186_get_reply(struct snd_sof_dev *sdev)
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{
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struct snd_sof_ipc_msg *msg = sdev->msg;
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struct sof_ipc_reply reply;
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int ret = 0;
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if (!msg) {
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dev_warn(sdev->dev, "unexpected ipc interrupt\n");
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return;
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}
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/* get reply */
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sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
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if (reply.error < 0) {
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memcpy(msg->reply_data, &reply, sizeof(reply));
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ret = reply.error;
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} else {
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/* reply has correct size? */
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if (reply.hdr.size != msg->reply_size) {
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dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
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msg->reply_size, reply.hdr.size);
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ret = -EINVAL;
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}
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/* read the message */
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if (msg->reply_size > 0)
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sof_mailbox_read(sdev, sdev->host_box.offset,
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msg->reply_data, msg->reply_size);
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}
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msg->reply_error = ret;
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}
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static void mt8186_dsp_handle_reply(struct mtk_adsp_ipc *ipc)
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{
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struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
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unsigned long flags;
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spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
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mt8186_get_reply(priv->sdev);
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snd_sof_ipc_reply(priv->sdev, 0);
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spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
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}
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static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc)
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{
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struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
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u32 p; /* panic code */
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int ret;
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/* Read the message from the debug box. */
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sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,
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&p, sizeof(p));
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/* Check to see if the message is a panic code 0x0dead*** */
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if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
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snd_sof_dsp_panic(priv->sdev, p, true);
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} else {
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snd_sof_ipc_msgs_rx(priv->sdev);
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/* tell DSP cmd is done */
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ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);
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if (ret)
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dev_err(priv->dev, "request send ipc failed");
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}
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}
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static struct mtk_adsp_ipc_ops dsp_ops = {
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.handle_reply = mt8186_dsp_handle_reply,
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.handle_request = mt8186_dsp_handle_request,
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};
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static int platform_parse_resource(struct platform_device *pdev, void *data)
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{
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struct resource *mmio;
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struct resource res;
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struct device_node *mem_region;
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struct device *dev = &pdev->dev;
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struct mtk_adsp_chip_info *adsp = data;
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int ret;
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mem_region = of_parse_phandle(dev->of_node, "memory-region", 0);
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if (!mem_region) {
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dev_err(dev, "no dma memory-region phandle\n");
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return -ENODEV;
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}
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ret = of_address_to_resource(mem_region, 0, &res);
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of_node_put(mem_region);
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if (ret) {
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dev_err(dev, "of_address_to_resource dma failed\n");
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return ret;
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}
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dev_dbg(dev, "DMA %pR\n", &res);
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ret = of_reserved_mem_device_init(dev);
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if (ret) {
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dev_err(dev, "of_reserved_mem_device_init failed\n");
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return ret;
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}
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mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
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if (!mem_region) {
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dev_err(dev, "no memory-region sysmem phandle\n");
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return -ENODEV;
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}
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ret = of_address_to_resource(mem_region, 0, &res);
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of_node_put(mem_region);
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if (ret) {
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dev_err(dev, "of_address_to_resource sysmem failed\n");
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return ret;
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}
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adsp->pa_dram = (phys_addr_t)res.start;
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if (adsp->pa_dram & DRAM_REMAP_MASK) {
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dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
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(u32)adsp->pa_dram);
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return -EINVAL;
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}
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adsp->dramsize = resource_size(&res);
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if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
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dev_err(dev, "adsp memory(%#x) is not enough for share\n",
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adsp->dramsize);
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return -EINVAL;
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}
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dev_dbg(dev, "dram pbase=%pa size=%#x\n", &adsp->pa_dram, adsp->dramsize);
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mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
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if (!mmio) {
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dev_err(dev, "no ADSP-CFG register resource\n");
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return -ENXIO;
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}
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adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
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if (IS_ERR(adsp->va_cfgreg))
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return PTR_ERR(adsp->va_cfgreg);
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adsp->pa_cfgreg = (phys_addr_t)mmio->start;
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adsp->cfgregsize = resource_size(mmio);
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dev_dbg(dev, "cfgreg pbase=%pa size=%#x\n", &adsp->pa_cfgreg, adsp->cfgregsize);
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mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
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if (!mmio) {
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dev_err(dev, "no SRAM resource\n");
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return -ENXIO;
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}
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adsp->pa_sram = (phys_addr_t)mmio->start;
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adsp->sramsize = resource_size(mmio);
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dev_dbg(dev, "sram pbase=%pa size=%#x\n", &adsp->pa_sram, adsp->sramsize);
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mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec");
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if (!mmio) {
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dev_err(dev, "no SEC register resource\n");
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return -ENXIO;
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}
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adsp->va_secreg = devm_ioremap_resource(dev, mmio);
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if (IS_ERR(adsp->va_secreg))
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return PTR_ERR(adsp->va_secreg);
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adsp->pa_secreg = (phys_addr_t)mmio->start;
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adsp->secregsize = resource_size(mmio);
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dev_dbg(dev, "secreg pbase=%pa size=%#x\n", &adsp->pa_secreg, adsp->secregsize);
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mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus");
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if (!mmio) {
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dev_err(dev, "no BUS register resource\n");
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return -ENXIO;
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}
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adsp->va_busreg = devm_ioremap_resource(dev, mmio);
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if (IS_ERR(adsp->va_busreg))
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return PTR_ERR(adsp->va_busreg);
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adsp->pa_busreg = (phys_addr_t)mmio->start;
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adsp->busregsize = resource_size(mmio);
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dev_dbg(dev, "busreg pbase=%pa size=%#x\n", &adsp->pa_busreg, adsp->busregsize);
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return 0;
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}
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static void adsp_sram_power_on(struct snd_sof_dev *sdev)
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{
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snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
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DSP_SRAM_POOL_PD_MASK, 0);
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}
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static void adsp_sram_power_off(struct snd_sof_dev *sdev)
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{
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snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
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DSP_SRAM_POOL_PD_MASK, DSP_SRAM_POOL_PD_MASK);
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}
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/* Init the basic DSP DRAM address */
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static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp)
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{
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u32 offset;
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offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
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adsp->dram_offset = offset;
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offset >>= DRAM_REMAP_SHIFT;
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dev_dbg(sdev->dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
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snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR, offset);
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snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR, offset);
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if (offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR) ||
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offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR)) {
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dev_err(sdev->dev, "emi remap fail\n");
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return -EIO;
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}
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return 0;
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}
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static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
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{
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struct device *dev = &pdev->dev;
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struct mtk_adsp_chip_info *adsp = data;
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u32 shared_size;
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/* remap shared-dram base to be non-cachable */
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shared_size = TOTAL_SIZE_SHARED_DRAM_FROM_TAIL;
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adsp->pa_shared_dram = adsp->pa_dram + adsp->dramsize - shared_size;
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if (adsp->va_dram) {
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adsp->shared_dram = adsp->va_dram + DSP_DRAM_SIZE - shared_size;
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} else {
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adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram,
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shared_size);
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if (!adsp->shared_dram) {
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dev_err(dev, "ioremap failed for shared DRAM\n");
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return -ENOMEM;
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}
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}
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dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n",
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adsp->shared_dram, &adsp->pa_shared_dram, shared_size);
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return 0;
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}
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static int mt8186_run(struct snd_sof_dev *sdev)
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{
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u32 adsp_bootup_addr;
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adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
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dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
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mt8186_sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
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return 0;
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}
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static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
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{
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struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
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struct adsp_priv *priv;
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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sdev->pdata->hw_pdata = priv;
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priv->dev = sdev->dev;
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priv->sdev = sdev;
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priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
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if (!priv->adsp)
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return -ENOMEM;
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ret = platform_parse_resource(pdev, priv->adsp);
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if (ret)
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return ret;
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sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
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priv->adsp->pa_sram,
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priv->adsp->sramsize);
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if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
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dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
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&priv->adsp->pa_sram, priv->adsp->sramsize);
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return -ENOMEM;
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}
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sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev,
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priv->adsp->pa_dram,
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priv->adsp->dramsize);
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if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
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dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
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&priv->adsp->pa_dram, priv->adsp->dramsize);
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return -ENOMEM;
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}
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priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
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ret = adsp_shared_base_ioremap(pdev, priv->adsp);
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if (ret) {
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dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n");
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return ret;
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}
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sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
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sdev->bar[DSP_SECREG_BAR] = priv->adsp->va_secreg;
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sdev->bar[DSP_BUSREG_BAR] = priv->adsp->va_busreg;
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sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
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sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
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/* set default mailbox offset for FW ready message */
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sdev->dsp_box.offset = mt8186_get_mailbox_offset(sdev);
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ret = adsp_memory_remap_init(sdev, priv->adsp);
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if (ret) {
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dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
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return ret;
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}
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/* enable adsp clock before touching registers */
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ret = mt8186_adsp_init_clock(sdev);
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if (ret) {
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dev_err(sdev->dev, "mt8186_adsp_init_clock failed\n");
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return ret;
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}
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ret = mt8186_adsp_clock_on(sdev);
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if (ret) {
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dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
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return ret;
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}
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adsp_sram_power_on(sdev);
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priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
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PLATFORM_DEVID_NONE,
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pdev, sizeof(*pdev));
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if (IS_ERR(priv->ipc_dev)) {
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ret = PTR_ERR(priv->ipc_dev);
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dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n");
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goto err_adsp_off;
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}
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priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
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if (!priv->dsp_ipc) {
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ret = -EPROBE_DEFER;
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dev_err(sdev->dev, "failed to get drvdata\n");
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goto exit_pdev_unregister;
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}
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mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
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priv->dsp_ipc->ops = &dsp_ops;
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return 0;
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exit_pdev_unregister:
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platform_device_unregister(priv->ipc_dev);
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err_adsp_off:
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adsp_sram_power_off(sdev);
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mt8186_adsp_clock_off(sdev);
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return ret;
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}
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static int mt8186_dsp_remove(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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platform_device_unregister(priv->ipc_dev);
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mt8186_sof_hifixdsp_shutdown(sdev);
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adsp_sram_power_off(sdev);
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mt8186_adsp_clock_off(sdev);
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return 0;
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}
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static int mt8186_dsp_shutdown(struct snd_sof_dev *sdev)
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{
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return snd_sof_suspend(sdev->dev);
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}
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static int mt8186_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
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{
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mt8186_sof_hifixdsp_shutdown(sdev);
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adsp_sram_power_off(sdev);
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mt8186_adsp_clock_off(sdev);
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return 0;
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}
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static int mt8186_dsp_resume(struct snd_sof_dev *sdev)
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{
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int ret;
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ret = mt8186_adsp_clock_on(sdev);
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if (ret) {
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dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
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return ret;
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}
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adsp_sram_power_on(sdev);
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return ret;
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}
|
|
|
|
/* on mt8186 there is 1 to 1 match between type and BAR idx */
|
|
static int mt8186_get_bar_index(struct snd_sof_dev *sdev, u32 type)
|
|
{
|
|
return type;
|
|
}
|
|
|
|
static int mt8186_pcm_hw_params(struct snd_sof_dev *sdev,
|
|
struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct snd_sof_platform_stream_params *platform_params)
|
|
{
|
|
platform_params->cont_update_posn = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static snd_pcm_uframes_t mt8186_pcm_pointer(struct snd_sof_dev *sdev,
|
|
struct snd_pcm_substream *substream)
|
|
{
|
|
int ret;
|
|
snd_pcm_uframes_t pos;
|
|
struct snd_sof_pcm *spcm;
|
|
struct sof_ipc_stream_posn posn;
|
|
struct snd_sof_pcm_stream *stream;
|
|
struct snd_soc_component *scomp = sdev->component;
|
|
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
|
|
|
|
spcm = snd_sof_find_spcm_dai(scomp, rtd);
|
|
if (!spcm) {
|
|
dev_warn_ratelimited(sdev->dev, "warn: can't find PCM with DAI ID %d\n",
|
|
rtd->dai_link->id);
|
|
return 0;
|
|
}
|
|
|
|
stream = &spcm->stream[substream->stream];
|
|
ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
|
|
if (ret < 0) {
|
|
dev_warn(sdev->dev, "failed to read stream position: %d\n", ret);
|
|
return 0;
|
|
}
|
|
|
|
memcpy(&stream->posn, &posn, sizeof(posn));
|
|
pos = spcm->stream[substream->stream].posn.host_posn;
|
|
pos = bytes_to_frames(substream->runtime, pos);
|
|
|
|
return pos;
|
|
}
|
|
|
|
static struct snd_soc_dai_driver mt8186_dai[] = {
|
|
{
|
|
.name = "SOF_DL1",
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
},
|
|
},
|
|
{
|
|
.name = "SOF_DL2",
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
},
|
|
},
|
|
{
|
|
.name = "SOF_UL1",
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
},
|
|
},
|
|
{
|
|
.name = "SOF_UL2",
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* mt8186 ops */
|
|
static struct snd_sof_dsp_ops sof_mt8186_ops = {
|
|
/* probe and remove */
|
|
.probe = mt8186_dsp_probe,
|
|
.remove = mt8186_dsp_remove,
|
|
.shutdown = mt8186_dsp_shutdown,
|
|
|
|
/* DSP core boot */
|
|
.run = mt8186_run,
|
|
|
|
/* Block IO */
|
|
.block_read = sof_block_read,
|
|
.block_write = sof_block_write,
|
|
|
|
/* Mailbox IO */
|
|
.mailbox_read = sof_mailbox_read,
|
|
.mailbox_write = sof_mailbox_write,
|
|
|
|
/* Register IO */
|
|
.write = sof_io_write,
|
|
.read = sof_io_read,
|
|
.write64 = sof_io_write64,
|
|
.read64 = sof_io_read64,
|
|
|
|
/* ipc */
|
|
.send_msg = mt8186_send_msg,
|
|
.get_mailbox_offset = mt8186_get_mailbox_offset,
|
|
.get_window_offset = mt8186_get_window_offset,
|
|
.ipc_msg_data = sof_ipc_msg_data,
|
|
.set_stream_data_offset = sof_set_stream_data_offset,
|
|
|
|
/* misc */
|
|
.get_bar_index = mt8186_get_bar_index,
|
|
|
|
/* stream callbacks */
|
|
.pcm_open = sof_stream_pcm_open,
|
|
.pcm_hw_params = mt8186_pcm_hw_params,
|
|
.pcm_pointer = mt8186_pcm_pointer,
|
|
.pcm_close = sof_stream_pcm_close,
|
|
|
|
/* firmware loading */
|
|
.load_firmware = snd_sof_load_firmware_memcpy,
|
|
|
|
/* Firmware ops */
|
|
.dsp_arch_ops = &sof_xtensa_arch_ops,
|
|
|
|
/* DAI drivers */
|
|
.drv = mt8186_dai,
|
|
.num_drv = ARRAY_SIZE(mt8186_dai),
|
|
|
|
/* Debug information */
|
|
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
|
|
|
|
/* PM */
|
|
.suspend = mt8186_dsp_suspend,
|
|
.resume = mt8186_dsp_resume,
|
|
|
|
/* ALSA HW info flags */
|
|
.hw_info = SNDRV_PCM_INFO_MMAP |
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
|
SNDRV_PCM_INFO_INTERLEAVED |
|
|
SNDRV_PCM_INFO_PAUSE |
|
|
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
|
|
};
|
|
|
|
static struct snd_sof_of_mach sof_mt8186_machs[] = {
|
|
{
|
|
.compatible = "mediatek,mt8186",
|
|
.sof_tplg_filename = "sof-mt8186.tplg",
|
|
},
|
|
{}
|
|
};
|
|
|
|
static const struct sof_dev_desc sof_of_mt8186_desc = {
|
|
.of_machines = sof_mt8186_machs,
|
|
.ipc_supported_mask = BIT(SOF_IPC),
|
|
.ipc_default = SOF_IPC,
|
|
.default_fw_path = {
|
|
[SOF_IPC] = "mediatek/sof",
|
|
},
|
|
.default_tplg_path = {
|
|
[SOF_IPC] = "mediatek/sof-tplg",
|
|
},
|
|
.default_fw_filename = {
|
|
[SOF_IPC] = "sof-mt8186.ri",
|
|
},
|
|
.nocodec_tplg_filename = "sof-mt8186-nocodec.tplg",
|
|
.ops = &sof_mt8186_ops,
|
|
};
|
|
|
|
static const struct sof_dev_desc sof_of_mt8188_desc = {
|
|
.ipc_supported_mask = BIT(SOF_IPC),
|
|
.ipc_default = SOF_IPC,
|
|
.default_fw_path = {
|
|
[SOF_IPC] = "mediatek/sof",
|
|
},
|
|
.default_tplg_path = {
|
|
[SOF_IPC] = "mediatek/sof-tplg",
|
|
},
|
|
.default_fw_filename = {
|
|
[SOF_IPC] = "sof-mt8188.ri",
|
|
},
|
|
.nocodec_tplg_filename = "sof-mt8188-nocodec.tplg",
|
|
.ops = &sof_mt8186_ops,
|
|
};
|
|
|
|
static const struct of_device_id sof_of_mt8186_ids[] = {
|
|
{ .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc},
|
|
{ .compatible = "mediatek,mt8188-dsp", .data = &sof_of_mt8188_desc},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids);
|
|
|
|
/* DT driver definition */
|
|
static struct platform_driver snd_sof_of_mt8186_driver = {
|
|
.probe = sof_of_probe,
|
|
.remove = sof_of_remove,
|
|
.shutdown = sof_of_shutdown,
|
|
.driver = {
|
|
.name = "sof-audio-of-mt8186",
|
|
.pm = &sof_of_pm,
|
|
.of_match_table = sof_of_mt8186_ids,
|
|
},
|
|
};
|
|
module_platform_driver(snd_sof_of_mt8186_driver);
|
|
|
|
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
|
|
MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON);
|
|
MODULE_LICENSE("Dual BSD/GPL");
|