795 lines
28 KiB
JSON
795 lines
28 KiB
JSON
[
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{
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"EventCode": "0x3515e",
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"EventName": "PM_MRK_BACK_BR_CMPL",
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"BriefDescription": "Marked branch instruction completed with a target address less than current instruction address",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2013a",
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"EventName": "PM_MRK_BRU_FIN",
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"BriefDescription": "bru marked instr finish",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x1016e",
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"EventName": "PM_MRK_BR_CMPL",
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"BriefDescription": "Branch Instruction completed",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x301e4",
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"EventName": "PM_MRK_BR_MPRED_CMPL",
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"BriefDescription": "Marked Branch Mispredicted",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x101e2",
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"EventName": "PM_MRK_BR_TAKEN_CMPL",
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"BriefDescription": "Marked Branch Taken completed",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d148",
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"EventName": "PM_MRK_DATA_FROM_DL2L3_MOD",
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"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d128",
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"EventName": "PM_MRK_DATA_FROM_DL2L3_MOD_CYC",
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"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x3d148",
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"EventName": "PM_MRK_DATA_FROM_DL2L3_SHR",
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"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2c128",
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"EventName": "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
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"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x3d14c",
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"EventName": "PM_MRK_DATA_FROM_DL4",
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"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2c12c",
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"EventName": "PM_MRK_DATA_FROM_DL4_CYC",
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"BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d14c",
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"EventName": "PM_MRK_DATA_FROM_DMEM",
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"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d12c",
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"EventName": "PM_MRK_DATA_FROM_DMEM_CYC",
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"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x1d142",
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"EventName": "PM_MRK_DATA_FROM_L2",
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"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x1d14e",
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"EventName": "PM_MRK_DATA_FROM_L2MISS",
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"BriefDescription": "Data cache reload L2 miss",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4c12e",
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"EventName": "PM_MRK_DATA_FROM_L2MISS_CYC",
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"BriefDescription": "Duration in cycles to reload from a location other than the local core's L2 due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4c122",
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"EventName": "PM_MRK_DATA_FROM_L2_CYC",
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"BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x3d140",
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"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
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"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2c120",
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"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
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"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d140",
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"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
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"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d120",
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"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC",
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"BriefDescription": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d140",
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"EventName": "PM_MRK_DATA_FROM_L2_MEPF",
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"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d120",
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"EventName": "PM_MRK_DATA_FROM_L2_MEPF_CYC",
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"BriefDescription": "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x1d140",
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"EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT",
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"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4c120",
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"EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC",
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"BriefDescription": "Duration in cycles to reload from local core's L2 without conflict due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d142",
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"EventName": "PM_MRK_DATA_FROM_L3",
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"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x201e4",
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"EventName": "PM_MRK_DATA_FROM_L3MISS",
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"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d12e",
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"EventName": "PM_MRK_DATA_FROM_L3MISS_CYC",
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"BriefDescription": "Duration in cycles to reload from a location other than the local core's L3 due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d122",
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"EventName": "PM_MRK_DATA_FROM_L3_CYC",
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"BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x3d142",
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"EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT",
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"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2c122",
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"EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC",
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"BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d142",
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"EventName": "PM_MRK_DATA_FROM_L3_MEPF",
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"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d122",
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"EventName": "PM_MRK_DATA_FROM_L3_MEPF_CYC",
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"BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x1d144",
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"EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT",
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"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4c124",
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"EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC",
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"BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x1d14c",
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"EventName": "PM_MRK_DATA_FROM_LL4",
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"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4c12c",
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"EventName": "PM_MRK_DATA_FROM_LL4_CYC",
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"BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d148",
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"EventName": "PM_MRK_DATA_FROM_LMEM",
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"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d128",
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"EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
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"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d14c",
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"EventName": "PM_MRK_DATA_FROM_MEMORY",
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"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d12c",
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"EventName": "PM_MRK_DATA_FROM_MEMORY_CYC",
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"BriefDescription": "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d14a",
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"EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE",
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"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d12a",
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"EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC",
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"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x1d148",
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"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE",
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"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4c128",
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"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
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"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d146",
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"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD",
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"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d126",
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"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
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"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x1d14a",
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"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR",
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"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4c12a",
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"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
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"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d14a",
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"EventName": "PM_MRK_DATA_FROM_RL4",
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"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d12a",
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"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
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"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x3d14a",
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"EventName": "PM_MRK_DATA_FROM_RMEM",
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"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2c12a",
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"EventName": "PM_MRK_DATA_FROM_RMEM_CYC",
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"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x40118",
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"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
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"BriefDescription": "Combined Intervention event",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x301e6",
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"EventName": "PM_MRK_DERAT_MISS",
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"BriefDescription": "Erat Miss (TLB Access) All page sizes",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4d154",
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"EventName": "PM_MRK_DERAT_MISS_16G",
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"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x3d154",
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"EventName": "PM_MRK_DERAT_MISS_16M",
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"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x1d156",
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"EventName": "PM_MRK_DERAT_MISS_4K",
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"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 4K",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d154",
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"EventName": "PM_MRK_DERAT_MISS_64K",
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"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x20132",
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"EventName": "PM_MRK_DFU_FIN",
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"BriefDescription": "Decimal Unit marked Instruction Finish",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4f148",
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"EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
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"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
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"PublicDescription": ""
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},
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|
{
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"EventCode": "0x3f148",
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"EventName": "PM_MRK_DPTEG_FROM_DL2L3_SHR",
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"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
|
|
"PublicDescription": ""
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|
},
|
|
{
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|
"EventCode": "0x3f14c",
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"EventName": "PM_MRK_DPTEG_FROM_DL4",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request",
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"PublicDescription": ""
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},
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|
{
|
|
"EventCode": "0x4f14c",
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"EventName": "PM_MRK_DPTEG_FROM_DMEM",
|
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"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request",
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"PublicDescription": ""
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},
|
|
{
|
|
"EventCode": "0x1f142",
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"EventName": "PM_MRK_DPTEG_FROM_L2",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request",
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"PublicDescription": ""
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},
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|
{
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"EventCode": "0x1f14e",
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"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request",
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"PublicDescription": ""
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},
|
|
{
|
|
"EventCode": "0x2f140",
|
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"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request",
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"PublicDescription": ""
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},
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|
{
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"EventCode": "0x1f140",
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"EventName": "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request",
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"PublicDescription": ""
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},
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{
|
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"EventCode": "0x4f142",
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"EventName": "PM_MRK_DPTEG_FROM_L3",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x4f14e",
|
|
"EventName": "PM_MRK_DPTEG_FROM_L3MISS",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x3f142",
|
|
"EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x2f142",
|
|
"EventName": "PM_MRK_DPTEG_FROM_L3_MEPF",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x1f144",
|
|
"EventName": "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x1f14c",
|
|
"EventName": "PM_MRK_DPTEG_FROM_LL4",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x2f148",
|
|
"EventName": "PM_MRK_DPTEG_FROM_LMEM",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x2f14c",
|
|
"EventName": "PM_MRK_DPTEG_FROM_MEMORY",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x4f14a",
|
|
"EventName": "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x1f148",
|
|
"EventName": "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x2f146",
|
|
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_MOD",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x1f14a",
|
|
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_SHR",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x2f14a",
|
|
"EventName": "PM_MRK_DPTEG_FROM_RL4",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x3f14a",
|
|
"EventName": "PM_MRK_DPTEG_FROM_RMEM",
|
|
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x401e4",
|
|
"EventName": "PM_MRK_DTLB_MISS",
|
|
"BriefDescription": "Marked dtlb miss",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x1d158",
|
|
"EventName": "PM_MRK_DTLB_MISS_16G",
|
|
"BriefDescription": "Marked Data TLB Miss page size 16G",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x4d156",
|
|
"EventName": "PM_MRK_DTLB_MISS_16M",
|
|
"BriefDescription": "Marked Data TLB Miss page size 16M",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x2d156",
|
|
"EventName": "PM_MRK_DTLB_MISS_4K",
|
|
"BriefDescription": "Marked Data TLB Miss page size 4k",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x3d156",
|
|
"EventName": "PM_MRK_DTLB_MISS_64K",
|
|
"BriefDescription": "Marked Data TLB Miss page size 64K",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x40154",
|
|
"EventName": "PM_MRK_FAB_RSP_BKILL",
|
|
"BriefDescription": "Marked store had to do a bkill",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x2f150",
|
|
"EventName": "PM_MRK_FAB_RSP_BKILL_CYC",
|
|
"BriefDescription": "cycles L2 RC took for a bkill",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x3015e",
|
|
"EventName": "PM_MRK_FAB_RSP_CLAIM_RTY",
|
|
"BriefDescription": "Sampled store did a rwitm and got a rty",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x30154",
|
|
"EventName": "PM_MRK_FAB_RSP_DCLAIM",
|
|
"BriefDescription": "Marked store had to do a dclaim",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x2f152",
|
|
"EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC",
|
|
"BriefDescription": "cycles L2 RC took for a dclaim",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x4015e",
|
|
"EventName": "PM_MRK_FAB_RSP_RD_RTY",
|
|
"BriefDescription": "Sampled L2 reads retry count",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x1015e",
|
|
"EventName": "PM_MRK_FAB_RSP_RD_T_INTV",
|
|
"BriefDescription": "Sampled Read got a T intervention",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x4f150",
|
|
"EventName": "PM_MRK_FAB_RSP_RWITM_CYC",
|
|
"BriefDescription": "cycles L2 RC took for a rwitm",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x2015e",
|
|
"EventName": "PM_MRK_FAB_RSP_RWITM_RTY",
|
|
"BriefDescription": "Sampled store did a rwitm and got a rty",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x20134",
|
|
"EventName": "PM_MRK_FXU_FIN",
|
|
"BriefDescription": "fxu marked instr finish",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x401e0",
|
|
"EventName": "PM_MRK_INST_CMPL",
|
|
"BriefDescription": "marked instruction completed",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x20130",
|
|
"EventName": "PM_MRK_INST_DECODED",
|
|
"BriefDescription": "marked instruction decoded",
|
|
"PublicDescription": "marked instruction decoded. Name from ISU?"
|
|
},
|
|
{
|
|
"EventCode": "0x101e0",
|
|
"EventName": "PM_MRK_INST_DISP",
|
|
"BriefDescription": "The thread has dispatched a randomly sampled marked instruction",
|
|
"PublicDescription": "Marked Instruction dispatched"
|
|
},
|
|
{
|
|
"EventCode": "0x30130",
|
|
"EventName": "PM_MRK_INST_FIN",
|
|
"BriefDescription": "marked instruction finished",
|
|
"PublicDescription": "marked instr finish any unit"
|
|
},
|
|
{
|
|
"EventCode": "0x401e6",
|
|
"EventName": "PM_MRK_INST_FROM_L3MISS",
|
|
"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet",
|
|
"PublicDescription": "n/a"
|
|
},
|
|
{
|
|
"EventCode": "0x10132",
|
|
"EventName": "PM_MRK_INST_ISSUED",
|
|
"BriefDescription": "Marked instruction issued",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x40134",
|
|
"EventName": "PM_MRK_INST_TIMEO",
|
|
"BriefDescription": "marked Instruction finish timeout (instruction lost)",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x101e4",
|
|
"EventName": "PM_MRK_L1_ICACHE_MISS",
|
|
"BriefDescription": "sampled Instruction suffered an icache Miss",
|
|
"PublicDescription": "Marked L1 Icache Miss"
|
|
},
|
|
{
|
|
"EventCode": "0x101ea",
|
|
"EventName": "PM_MRK_L1_RELOAD_VALID",
|
|
"BriefDescription": "Marked demand reload",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x20114",
|
|
"EventName": "PM_MRK_L2_RC_DISP",
|
|
"BriefDescription": "Marked Instruction RC dispatched in L2",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x3012a",
|
|
"EventName": "PM_MRK_L2_RC_DONE",
|
|
"BriefDescription": "Marked RC done",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x40116",
|
|
"EventName": "PM_MRK_LARX_FIN",
|
|
"BriefDescription": "Larx finished",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x1013e",
|
|
"EventName": "PM_MRK_LD_MISS_EXPOSED_CYC",
|
|
"BriefDescription": "Marked Load exposed Miss cycles",
|
|
"PublicDescription": "Marked Load exposed Miss (use edge detect to count #)"
|
|
},
|
|
{
|
|
"EventCode": "0x201e2",
|
|
"EventName": "PM_MRK_LD_MISS_L1",
|
|
"BriefDescription": "Marked DL1 Demand Miss counted at exec time",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x4013e",
|
|
"EventName": "PM_MRK_LD_MISS_L1_CYC",
|
|
"BriefDescription": "Marked ld latency",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x40132",
|
|
"EventName": "PM_MRK_LSU_FIN",
|
|
"BriefDescription": "lsu marked instr finish",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x20112",
|
|
"EventName": "PM_MRK_NTF_FIN",
|
|
"BriefDescription": "Marked next to finish instruction finished",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x1d15e",
|
|
"EventName": "PM_MRK_RUN_CYC",
|
|
"BriefDescription": "Marked run cycles",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x3013e",
|
|
"EventName": "PM_MRK_STALL_CMPLU_CYC",
|
|
"BriefDescription": "Marked Group completion Stall",
|
|
"PublicDescription": "Marked Group Completion Stall cycles (use edge detect to count #)"
|
|
},
|
|
{
|
|
"EventCode": "0x3e158",
|
|
"EventName": "PM_MRK_STCX_FAIL",
|
|
"BriefDescription": "marked stcx failed",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x10134",
|
|
"EventName": "PM_MRK_ST_CMPL",
|
|
"BriefDescription": "marked store completed and sent to nest",
|
|
"PublicDescription": "Marked store completed"
|
|
},
|
|
{
|
|
"EventCode": "0x30134",
|
|
"EventName": "PM_MRK_ST_CMPL_INT",
|
|
"BriefDescription": "marked store finished with intervention",
|
|
"PublicDescription": "marked store complete (data home) with intervention"
|
|
},
|
|
{
|
|
"EventCode": "0x3f150",
|
|
"EventName": "PM_MRK_ST_DRAIN_TO_L2DISP_CYC",
|
|
"BriefDescription": "cycles to drain st from core to L2",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x3012c",
|
|
"EventName": "PM_MRK_ST_FWD",
|
|
"BriefDescription": "Marked st forwards",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x1f150",
|
|
"EventName": "PM_MRK_ST_L2DISP_TO_CMPL_CYC",
|
|
"BriefDescription": "cycles from L2 rc disp to l2 rc completion",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x20138",
|
|
"EventName": "PM_MRK_ST_NEST",
|
|
"BriefDescription": "Marked store sent to nest",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x30132",
|
|
"EventName": "PM_MRK_VSU_FIN",
|
|
"BriefDescription": "VSU marked instr finish",
|
|
"PublicDescription": "vsu (fpu) marked instr finish"
|
|
},
|
|
{
|
|
"EventCode": "0x3d15e",
|
|
"EventName": "PM_MULT_MRK",
|
|
"BriefDescription": "mult marked instr",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x15152",
|
|
"EventName": "PM_SYNC_MRK_BR_LINK",
|
|
"BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x1515c",
|
|
"EventName": "PM_SYNC_MRK_BR_MPRED",
|
|
"BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x15156",
|
|
"EventName": "PM_SYNC_MRK_FX_DIVIDE",
|
|
"BriefDescription": "Marked fixed point divide that can cause a synchronous interrupt",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x15158",
|
|
"EventName": "PM_SYNC_MRK_L2HIT",
|
|
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x1515a",
|
|
"EventName": "PM_SYNC_MRK_L2MISS",
|
|
"BriefDescription": "Marked L2 Miss that can throw a synchronous interrupt",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x15154",
|
|
"EventName": "PM_SYNC_MRK_L3MISS",
|
|
"BriefDescription": "Marked L3 misses that can throw a synchronous interrupt",
|
|
"PublicDescription": ""
|
|
},
|
|
{
|
|
"EventCode": "0x15150",
|
|
"EventName": "PM_SYNC_MRK_PROBE_NOP",
|
|
"BriefDescription": "Marked probeNops which can cause synchronous interrupts",
|
|
"PublicDescription": ""
|
|
}
|
|
]
|