linux-zen-server/tools/perf/pmu-events/arch/x86/amdzen4/memory.json

[
  {
    "EventName": "ls_bad_status2.stli_other",
    "EventCode": "0x24",
    "BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store).",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_dispatch.ld_dispatch",
    "EventCode": "0x29",
    "BriefDescription": "Number of memory load operations dispatched to the load-store unit.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_dispatch.store_dispatch",
    "EventCode": "0x29",
    "BriefDescription": "Number of memory store operations dispatched to the load-store unit.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_dispatch.ld_st_dispatch",
    "EventCode": "0x29",
    "BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_stlf",
    "EventCode": "0x35",
    "BriefDescription": "Store-to-load-forward (STLF) hits."
  },
  {
    "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
    "EventCode": "0x37",
    "BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
    "UMask": "0x08"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.",
    "UMask": "0x10"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
    "UMask": "0x20"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages.",
    "UMask": "0x40"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages.",
    "UMask": "0x80"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.all_l2_miss",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes.",
    "UMask": "0xf0"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.all",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses for all page sizes.",
    "UMask": "0xff"
  },
  {
    "EventName": "ls_misal_loads.ma64",
    "EventCode": "0x47",
    "BriefDescription": "64B misaligned (cacheline crossing) loads.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_misal_loads.ma4k",
    "EventCode": "0x47",
    "BriefDescription": "4kB misaligned (page crossing) loads.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_tlb_flush.all",
    "EventCode": "0x78",
    "BriefDescription": "All TLB Flushes.",
    "UMask": "0xff"
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_hit",
    "EventCode": "0x84",
    "BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
    "EventCode": "0x85",
    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.",
    "UMask": "0x01"
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
    "EventCode": "0x85",
    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.",
    "UMask": "0x02"
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
    "EventCode": "0x85",
    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.",
    "UMask": "0x04"
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
    "EventCode": "0x85",
    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
    "UMask": "0x08"
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
    "EventCode": "0x85",
    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.",
    "UMask": "0x0f"
  },
  {
    "EventName": "bp_l1_tlb_fetch_hit.if4k",
    "EventCode": "0x94",
    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
    "UMask": "0x01"
  },
  {
    "EventName": "bp_l1_tlb_fetch_hit.if2m",
    "EventCode": "0x94",
    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
    "UMask": "0x02"
  },
  {
    "EventName": "bp_l1_tlb_fetch_hit.if1g",
    "EventCode": "0x94",
    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
    "UMask": "0x04"
  },
  {
    "EventName": "bp_l1_tlb_fetch_hit.all",
    "EventCode": "0x94",
    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
    "UMask": "0x07"
  }
]