35 lines
1.2 KiB
JSON
35 lines
1.2 KiB
JSON
[
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{
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"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
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"EventCode": "0x12",
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"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "100003",
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"UMask": "0xe",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
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"EventCode": "0x13",
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"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "100003",
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"UMask": "0xe",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "200003",
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"UMask": "0xe",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
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"EventCode": "0x11",
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"EventName": "ITLB_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "100003",
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"UMask": "0xe",
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"Unit": "cpu_core"
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}
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]
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