235 lines
7.6 KiB
C
235 lines
7.6 KiB
C
/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
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/*
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* rseq-x86.h
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*
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* (C) Copyright 2016-2022 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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*/
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#ifndef RSEQ_H
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#error "Never use <rseq-x86.h> directly; include <rseq.h> instead."
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#endif
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#include <stdint.h>
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/*
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* RSEQ_SIG is used with the following reserved undefined instructions, which
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* trap in user-space:
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*
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* x86-32: 0f b9 3d 53 30 05 53 ud1 0x53053053,%edi
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* x86-64: 0f b9 3d 53 30 05 53 ud1 0x53053053(%rip),%edi
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*/
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#define RSEQ_SIG 0x53053053
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/*
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* Due to a compiler optimization bug in gcc-8 with asm goto and TLS asm input
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* operands, we cannot use "m" input operands, and rather pass the __rseq_abi
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* address through a "r" input operand.
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*/
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/* Offset of cpu_id, rseq_cs, and mm_cid fields in struct rseq. */
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#define RSEQ_CPU_ID_OFFSET 4
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#define RSEQ_CS_OFFSET 8
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#define RSEQ_MM_CID_OFFSET 24
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#ifdef __x86_64__
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#define RSEQ_ASM_TP_SEGMENT %%fs
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#define rseq_smp_mb() \
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__asm__ __volatile__ ("lock; addl $0,-128(%%rsp)" ::: "memory", "cc")
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#define rseq_smp_rmb() rseq_barrier()
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#define rseq_smp_wmb() rseq_barrier()
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#define rseq_smp_load_acquire(p) \
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__extension__ ({ \
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__typeof(*p) ____p1 = RSEQ_READ_ONCE(*p); \
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rseq_barrier(); \
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____p1; \
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})
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#define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb()
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#define rseq_smp_store_release(p, v) \
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do { \
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rseq_barrier(); \
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RSEQ_WRITE_ONCE(*p, v); \
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} while (0)
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#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, \
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start_ip, post_commit_offset, abort_ip) \
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".pushsection __rseq_cs, \"aw\"\n\t" \
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".balign 32\n\t" \
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__rseq_str(label) ":\n\t" \
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".long " __rseq_str(version) ", " __rseq_str(flags) "\n\t" \
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".quad " __rseq_str(start_ip) ", " __rseq_str(post_commit_offset) ", " __rseq_str(abort_ip) "\n\t" \
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".popsection\n\t" \
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".pushsection __rseq_cs_ptr_array, \"aw\"\n\t" \
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".quad " __rseq_str(label) "b\n\t" \
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".popsection\n\t"
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#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \
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__RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \
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(post_commit_ip - start_ip), abort_ip)
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/*
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* Exit points of a rseq critical section consist of all instructions outside
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* of the critical section where a critical section can either branch to or
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* reach through the normal course of its execution. The abort IP and the
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* post-commit IP are already part of the __rseq_cs section and should not be
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* explicitly defined as additional exit points. Knowing all exit points is
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* useful to assist debuggers stepping over the critical section.
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*/
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#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \
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".pushsection __rseq_exit_point_array, \"aw\"\n\t" \
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".quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n\t" \
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".popsection\n\t"
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#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
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RSEQ_INJECT_ASM(1) \
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"leaq " __rseq_str(cs_label) "(%%rip), %%rax\n\t" \
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"movq %%rax, " __rseq_str(rseq_cs) "\n\t" \
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__rseq_str(label) ":\n\t"
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#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \
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RSEQ_INJECT_ASM(2) \
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"cmpl %[" __rseq_str(cpu_id) "], " __rseq_str(current_cpu_id) "\n\t" \
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"jnz " __rseq_str(label) "\n\t"
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#define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label) \
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".pushsection __rseq_failure, \"ax\"\n\t" \
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/* Disassembler-friendly signature: ud1 <sig>(%rip),%edi. */ \
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".byte 0x0f, 0xb9, 0x3d\n\t" \
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".long " __rseq_str(RSEQ_SIG) "\n\t" \
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__rseq_str(label) ":\n\t" \
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teardown \
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"jmp %l[" __rseq_str(abort_label) "]\n\t" \
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".popsection\n\t"
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#define RSEQ_ASM_DEFINE_CMPFAIL(label, teardown, cmpfail_label) \
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".pushsection __rseq_failure, \"ax\"\n\t" \
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__rseq_str(label) ":\n\t" \
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teardown \
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"jmp %l[" __rseq_str(cmpfail_label) "]\n\t" \
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".popsection\n\t"
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#elif defined(__i386__)
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#define RSEQ_ASM_TP_SEGMENT %%gs
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#define rseq_smp_mb() \
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__asm__ __volatile__ ("lock; addl $0,-128(%%esp)" ::: "memory", "cc")
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#define rseq_smp_rmb() \
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__asm__ __volatile__ ("lock; addl $0,-128(%%esp)" ::: "memory", "cc")
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#define rseq_smp_wmb() \
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__asm__ __volatile__ ("lock; addl $0,-128(%%esp)" ::: "memory", "cc")
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#define rseq_smp_load_acquire(p) \
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__extension__ ({ \
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__typeof(*p) ____p1 = RSEQ_READ_ONCE(*p); \
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rseq_smp_mb(); \
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____p1; \
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})
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#define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb()
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#define rseq_smp_store_release(p, v) \
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do { \
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rseq_smp_mb(); \
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RSEQ_WRITE_ONCE(*p, v); \
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} while (0)
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/*
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* Use eax as scratch register and take memory operands as input to
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* lessen register pressure. Especially needed when compiling in O0.
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*/
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#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, \
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start_ip, post_commit_offset, abort_ip) \
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".pushsection __rseq_cs, \"aw\"\n\t" \
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".balign 32\n\t" \
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__rseq_str(label) ":\n\t" \
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".long " __rseq_str(version) ", " __rseq_str(flags) "\n\t" \
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".long " __rseq_str(start_ip) ", 0x0, " __rseq_str(post_commit_offset) ", 0x0, " __rseq_str(abort_ip) ", 0x0\n\t" \
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".popsection\n\t" \
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".pushsection __rseq_cs_ptr_array, \"aw\"\n\t" \
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".long " __rseq_str(label) "b, 0x0\n\t" \
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".popsection\n\t"
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#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \
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__RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \
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(post_commit_ip - start_ip), abort_ip)
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/*
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* Exit points of a rseq critical section consist of all instructions outside
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* of the critical section where a critical section can either branch to or
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* reach through the normal course of its execution. The abort IP and the
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* post-commit IP are already part of the __rseq_cs section and should not be
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* explicitly defined as additional exit points. Knowing all exit points is
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* useful to assist debuggers stepping over the critical section.
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*/
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#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \
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".pushsection __rseq_exit_point_array, \"aw\"\n\t" \
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".long " __rseq_str(start_ip) ", 0x0, " __rseq_str(exit_ip) ", 0x0\n\t" \
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".popsection\n\t"
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#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
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RSEQ_INJECT_ASM(1) \
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"movl $" __rseq_str(cs_label) ", " __rseq_str(rseq_cs) "\n\t" \
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__rseq_str(label) ":\n\t"
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#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \
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RSEQ_INJECT_ASM(2) \
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"cmpl %[" __rseq_str(cpu_id) "], " __rseq_str(current_cpu_id) "\n\t" \
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"jnz " __rseq_str(label) "\n\t"
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#define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label) \
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".pushsection __rseq_failure, \"ax\"\n\t" \
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/* Disassembler-friendly signature: ud1 <sig>,%edi. */ \
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".byte 0x0f, 0xb9, 0x3d\n\t" \
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".long " __rseq_str(RSEQ_SIG) "\n\t" \
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__rseq_str(label) ":\n\t" \
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teardown \
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"jmp %l[" __rseq_str(abort_label) "]\n\t" \
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".popsection\n\t"
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#define RSEQ_ASM_DEFINE_CMPFAIL(label, teardown, cmpfail_label) \
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".pushsection __rseq_failure, \"ax\"\n\t" \
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__rseq_str(label) ":\n\t" \
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teardown \
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"jmp %l[" __rseq_str(cmpfail_label) "]\n\t" \
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".popsection\n\t"
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#endif
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/* Per-cpu-id indexing. */
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#define RSEQ_TEMPLATE_CPU_ID
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-x86-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#define RSEQ_TEMPLATE_MO_RELEASE
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#include "rseq-x86-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELEASE
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#undef RSEQ_TEMPLATE_CPU_ID
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/* Per-mm-cid indexing. */
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#define RSEQ_TEMPLATE_MM_CID
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-x86-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#define RSEQ_TEMPLATE_MO_RELEASE
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#include "rseq-x86-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELEASE
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#undef RSEQ_TEMPLATE_MM_CID
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/* APIs which are not based on cpu ids. */
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#define RSEQ_TEMPLATE_CPU_ID_NONE
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-x86-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#undef RSEQ_TEMPLATE_CPU_ID_NONE
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