295 lines
7.2 KiB
YAML
295 lines
7.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Adreno or Snapdragon GPUs
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maintainers:
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- Rob Clark <robdclark@gmail.com>
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properties:
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compatible:
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oneOf:
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- description: |
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The driver is parsing the compat string for Adreno to
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figure out the gpu-id and patch level.
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items:
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- pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
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- const: qcom,adreno
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- description: |
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The driver is parsing the compat string for Imageon to
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figure out the gpu-id and patch level.
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items:
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- pattern: '^amd,imageon-200\.[0-1]$'
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- const: amd,imageon
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clocks: true
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clock-names: true
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reg:
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minItems: 1
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maxItems: 3
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reg-names:
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minItems: 1
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items:
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- const: kgsl_3d0_reg_memory
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- const: cx_mem
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- const: cx_dbgc
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interrupts:
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maxItems: 1
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interrupt-names:
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maxItems: 1
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interconnects:
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minItems: 1
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maxItems: 2
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interconnect-names:
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minItems: 1
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items:
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- const: gfx-mem
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- const: ocmem
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iommus:
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minItems: 1
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maxItems: 64
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sram:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 4
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items:
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maxItems: 1
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description: |
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phandles to one or more reserved on-chip SRAM regions.
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phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
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a4xx Snapdragon SoCs. See
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Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
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operating-points-v2: true
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opp-table:
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type: object
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power-domains:
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maxItems: 1
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zap-shader:
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type: object
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additionalProperties: false
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description: |
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For a5xx and a6xx devices this node contains a memory-region that
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points to reserved memory to store the zap shader that can be used to
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help bring the GPU out of secure mode.
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properties:
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memory-region:
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maxItems: 1
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firmware-name:
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description: |
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Default name of the firmware to load to the remote processor.
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"#cooling-cells":
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const: 2
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nvmem-cell-names:
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maxItems: 1
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nvmem-cells:
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description: efuse registers
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maxItems: 1
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qcom,gmu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: |
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For GMU attached devices a phandle to the GMU device that will
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control the power for the GPU.
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 7
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clock-names:
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items:
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anyOf:
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- const: core
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description: GPU Core clock
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- const: iface
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description: GPU Interface clock
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- const: mem
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description: GPU Memory clock
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- const: mem_iface
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description: GPU Memory Interface clock
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- const: alt_mem_iface
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description: GPU Alternative Memory Interface clock
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- const: gfx3d
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description: GPU 3D engine clock
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- const: rbbmtimer
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description: GPU RBBM Timer for Adreno 5xx series
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- const: rbcpr
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description: GPU RB Core Power Reduction clock
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minItems: 2
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maxItems: 7
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required:
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- clocks
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- clock-names
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- if:
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properties:
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compatible:
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contains:
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pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
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then: # Since Adreno 6xx series clocks should be defined in GMU
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properties:
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clocks: false
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clock-names: false
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examples:
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- |
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// Example a3xx/4xx:
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#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gpu: gpu@fdb00000 {
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compatible = "qcom,adreno-330.2", "qcom,adreno";
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reg = <0xfdb00000 0x10000>;
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reg-names = "kgsl_3d0_reg_memory";
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clock-names = "core", "iface", "mem_iface";
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clocks = <&mmcc OXILI_GFX3D_CLK>,
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<&mmcc OXILICX_AHB_CLK>,
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<&mmcc OXILICX_AXI_CLK>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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sram = <&gpu_sram>;
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power-domains = <&mmcc OXILICX_GDSC>;
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operating-points-v2 = <&gpu_opp_table>;
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iommus = <&gpu_iommu 0>;
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#cooling-cells = <2>;
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};
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ocmem@fdd00000 {
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compatible = "qcom,msm8974-ocmem";
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reg = <0xfdd00000 0x2000>,
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<0xfec00000 0x180000>;
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reg-names = "ctrl", "mem";
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clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
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<&mmcc OCMEMCX_OCMEMNOC_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xfec00000 0x100000>;
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gpu_sram: gpu-sram@0 {
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reg = <0x0 0x100000>;
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};
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};
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- |
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// Example a6xx (with GMU):
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#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sdm845.h>
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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zap_shader_region: gpu@8f200000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x90b00000 0x0 0xa00000>;
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no-map;
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};
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};
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gpu@5000000 {
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compatible = "qcom,adreno-630.2", "qcom,adreno";
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reg = <0x5000000 0x40000>, <0x509e000 0x10>;
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reg-names = "kgsl_3d0_reg_memory", "cx_mem";
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#cooling-cells = <2>;
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interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&adreno_smmu 0>;
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operating-points-v2 = <&gpu_opp_table>;
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interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
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interconnect-names = "gfx-mem";
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qcom,gmu = <&gmu>;
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gpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-430000000 {
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opp-hz = /bits/ 64 <430000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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opp-peak-kBps = <5412000>;
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};
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opp-355000000 {
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opp-hz = /bits/ 64 <355000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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opp-peak-kBps = <3072000>;
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};
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opp-267000000 {
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opp-hz = /bits/ 64 <267000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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opp-peak-kBps = <3072000>;
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};
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opp-180000000 {
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opp-hz = /bits/ 64 <180000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
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opp-peak-kBps = <1804000>;
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};
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};
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zap-shader {
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memory-region = <&zap_shader_region>;
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firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
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};
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};
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