431 lines
12 KiB
YAML
431 lines
12 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra host1x controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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description: The host1x top-level node defines a number of children, each
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representing one of the host1x client modules defined in this binding.
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properties:
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compatible:
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oneOf:
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- enum:
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- nvidia,tegra20-host1x
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- nvidia,tegra30-host1x
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- nvidia,tegra114-host1x
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- nvidia,tegra124-host1x
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- nvidia,tegra210-host1x
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- nvidia,tegra186-host1x
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- nvidia,tegra194-host1x
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- nvidia,tegra234-host1x
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- items:
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- const: nvidia,tegra132-host1x
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- const: nvidia,tegra124-host1x
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reg:
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minItems: 1
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maxItems: 3
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reg-names:
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minItems: 1
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maxItems: 3
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interrupts:
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minItems: 1
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maxItems: 9
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interrupt-names:
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minItems: 1
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maxItems: 9
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'#address-cells':
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description: The number of cells used to represent physical base addresses
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in the host1x address space.
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enum: [1, 2]
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'#size-cells':
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description: The number of cells used to represent the size of an address
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range in the host1x address space.
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enum: [1, 2]
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ranges:
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maxItems: 1
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clocks:
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description: Must contain one entry, for the module clock. See
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../clocks/clock-bindings.txt for details.
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clock-names:
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items:
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- const: host1x
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resets:
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minItems: 1 # MC reset is optional on Tegra186 and later
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items:
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- description: module reset
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- description: memory client hotflush reset
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reset-names:
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minItems: 1 # MC reset is optional on Tegra186 and later
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items:
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- const: host1x
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- const: mc
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iommus:
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maxItems: 1
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interconnects:
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items:
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- description: memory read client for host1x
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interconnect-names:
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items:
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- const: dma-mem # read
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operating-points-v2: true
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power-domains:
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items:
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- description: phandle to the HEG or core power domain
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required:
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- compatible
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- interrupts
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- interrupt-names
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- '#address-cells'
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- '#size-cells'
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- ranges
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- reg
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- clocks
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- clock-names
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unevaluatedProperties:
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type: object
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra20-host1x
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- nvidia,tegra30-host1x
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- nvidia,tegra114-host1x
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- nvidia,tegra124-host1x
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- nvidia,tegra210-host1x
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then:
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properties:
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interrupts:
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items:
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- description: host1x syncpoint interrupt
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- description: host1x general interrupt
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interrupt-names:
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items:
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- const: syncpt
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- const: host1x
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required:
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- resets
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- reset-names
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra186-host1x
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- nvidia,tegra194-host1x
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then:
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properties:
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reg-names:
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items:
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- const: hypervisor
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- const: vm
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reg:
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items:
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- description: region used by the hypervisor
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- description: region assigned to the virtual machine
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resets:
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maxItems: 1
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reset-names:
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maxItems: 1
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interrupts:
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items:
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- description: host1x syncpoint interrupt
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- description: host1x general interrupt
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interrupt-names:
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items:
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- const: syncpt
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- const: host1x
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iommu-map:
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description: Specification of stream IDs available for memory context device
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use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
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usable stream IDs.
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required:
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- reg-names
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra234-host1x
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then:
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properties:
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reg-names:
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items:
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- const: common
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- const: hypervisor
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- const: vm
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reg:
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items:
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- description: region used by host1x server
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- description: region used by the hypervisor
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- description: region assigned to the virtual machine
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interrupts:
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items:
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- description: host1x syncpoint interrupt 0
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- description: host1x syncpoint interrupt 1
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- description: host1x syncpoint interrupt 2
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- description: host1x syncpoint interrupt 3
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- description: host1x syncpoint interrupt 4
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- description: host1x syncpoint interrupt 5
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- description: host1x syncpoint interrupt 6
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- description: host1x syncpoint interrupt 7
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- description: host1x general interrupt
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interrupt-names:
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items:
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- const: syncpt0
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- const: syncpt1
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- const: syncpt2
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- const: syncpt3
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- const: syncpt4
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- const: syncpt5
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- const: syncpt6
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- const: syncpt7
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- const: host1x
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iommu-map:
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description: Specification of stream IDs available for memory context device
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use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
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usable stream IDs.
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required:
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- reg-names
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examples:
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- |
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#include <dt-bindings/clock/tegra20-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/memory/tegra20-mc.h>
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host1x@50000000 {
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compatible = "nvidia,tegra20-host1x";
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reg = <0x50000000 0x00024000>;
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interrupts = <0 65 0x04>, /* mpcore syncpt */
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<0 67 0x04>; /* mpcore general */
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interrupt-names = "syncpt", "host1x";
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clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
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clock-names = "host1x";
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resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
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reset-names = "host1x", "mc";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x54000000 0x54000000 0x04000000>;
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mpe@54040000 {
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compatible = "nvidia,tegra20-mpe";
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reg = <0x54040000 0x00040000>;
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interrupts = <0 68 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_MPE>;
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resets = <&tegra_car 60>;
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reset-names = "mpe";
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};
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vi@54080000 {
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compatible = "nvidia,tegra20-vi";
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reg = <0x54080000 0x00040000>;
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interrupts = <0 69 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_VI>;
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resets = <&tegra_car 100>;
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reset-names = "vi";
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};
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epp@540c0000 {
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compatible = "nvidia,tegra20-epp";
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reg = <0x540c0000 0x00040000>;
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interrupts = <0 70 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_EPP>;
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resets = <&tegra_car 19>;
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reset-names = "epp";
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};
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isp@54100000 {
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compatible = "nvidia,tegra20-isp";
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reg = <0x54100000 0x00040000>;
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interrupts = <0 71 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_ISP>;
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resets = <&tegra_car 23>;
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reset-names = "isp";
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};
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gr2d@54140000 {
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compatible = "nvidia,tegra20-gr2d";
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reg = <0x54140000 0x00040000>;
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interrupts = <0 72 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_GR2D>;
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resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
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reset-names = "2d", "mc";
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};
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gr3d@54180000 {
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compatible = "nvidia,tegra20-gr3d";
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reg = <0x54180000 0x00040000>;
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clocks = <&tegra_car TEGRA20_CLK_GR3D>;
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resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
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reset-names = "3d", "mc";
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};
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dc@54200000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54200000 0x00040000>;
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interrupts = <0 73 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_DISP1>;
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clock-names = "dc";
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resets = <&tegra_car 27>;
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reset-names = "dc";
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rgb {
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};
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};
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dc@54240000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54240000 0x00040000>;
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interrupts = <0 74 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_DISP2>;
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clock-names = "dc";
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resets = <&tegra_car 26>;
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reset-names = "dc";
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rgb {
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};
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};
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hdmi@54280000 {
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compatible = "nvidia,tegra20-hdmi";
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reg = <0x54280000 0x00040000>;
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interrupts = <0 75 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_HDMI>,
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<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
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clock-names = "hdmi", "parent";
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resets = <&tegra_car 51>;
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reset-names = "hdmi";
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hdmi-supply = <&vdd_5v0_hdmi>;
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pll-supply = <&vdd_hdmi_pll>;
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vdd-supply = <&vdd_3v3_hdmi>;
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nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
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};
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tvo@542c0000 {
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compatible = "nvidia,tegra20-tvo";
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reg = <0x542c0000 0x00040000>;
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interrupts = <0 76 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_TVO>;
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};
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dsi@54300000 {
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compatible = "nvidia,tegra20-dsi";
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reg = <0x54300000 0x00040000>;
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clocks = <&tegra_car TEGRA20_CLK_DSI>,
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<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
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clock-names = "dsi", "parent";
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resets = <&tegra_car 48>;
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reset-names = "dsi";
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};
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};
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/tegra210-mc.h>
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host1x@50000000 {
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compatible = "nvidia,tegra210-host1x";
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reg = <0x50000000 0x00024000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
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interrupt-names = "syncpt", "host1x";
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clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
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clock-names = "host1x";
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resets = <&tegra_car 28>;
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reset-names = "host1x";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x54000000 0x54000000 0x01000000>;
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iommus = <&mc TEGRA_SWGROUP_HC>;
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vi@54080000 {
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compatible = "nvidia,tegra210-vi";
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reg = <0x54080000 0x00000700>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
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clocks = <&tegra_car TEGRA210_CLK_VI>;
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power-domains = <&pd_venc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x54080000 0x2000>;
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csi@838 {
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compatible = "nvidia,tegra210-csi";
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reg = <0x838 0x1300>;
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assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
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<&tegra_car TEGRA210_CLK_CILCD>,
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<&tegra_car TEGRA210_CLK_CILE>,
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<&tegra_car TEGRA210_CLK_CSI_TPG>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_PLL_P>;
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assigned-clock-rates = <102000000>,
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<102000000>,
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<102000000>,
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<972000000>;
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clocks = <&tegra_car TEGRA210_CLK_CSI>,
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<&tegra_car TEGRA210_CLK_CILAB>,
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<&tegra_car TEGRA210_CLK_CILCD>,
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<&tegra_car TEGRA210_CLK_CILE>,
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<&tegra_car TEGRA210_CLK_CSI_TPG>;
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clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
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power-domains = <&pd_sor>;
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};
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};
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};
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