75 lines
2.1 KiB
YAML
75 lines
2.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Common properties for LPDDR types
|
|
|
|
description:
|
|
Different LPDDR types generally use the same properties and only differ in the
|
|
range of legal values for each. This file defines the common parts that can be
|
|
reused for each type. Nodes using this schema should generally be nested under
|
|
an LPDDR channel node.
|
|
|
|
maintainers:
|
|
- Krzysztof Kozlowski <krzk@kernel.org>
|
|
|
|
properties:
|
|
compatible:
|
|
description:
|
|
Compatible strings can be either explicit vendor names and part numbers
|
|
(e.g. elpida,ECB240ABACN), or generated strings of the form
|
|
lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID
|
|
(from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are
|
|
formatted in lower case hexadecimal representation with leading zeroes.
|
|
The latter form can be useful when LPDDR nodes are created at runtime by
|
|
boot firmware that doesn't have access to static part number information.
|
|
|
|
reg:
|
|
description:
|
|
The rank number of this LPDDR rank when used as a subnode to an LPDDR
|
|
channel.
|
|
minimum: 0
|
|
maximum: 3
|
|
|
|
revision-id:
|
|
$ref: /schemas/types.yaml#/definitions/uint32-array
|
|
description:
|
|
Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
|
|
maxItems: 2
|
|
items:
|
|
minimum: 0
|
|
maximum: 255
|
|
|
|
density:
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
description:
|
|
Density in megabits of SDRAM chip. Decoded from Mode Register 8.
|
|
enum:
|
|
- 64
|
|
- 128
|
|
- 256
|
|
- 512
|
|
- 1024
|
|
- 2048
|
|
- 3072
|
|
- 4096
|
|
- 6144
|
|
- 8192
|
|
- 12288
|
|
- 16384
|
|
- 24576
|
|
- 32768
|
|
|
|
io-width:
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
description:
|
|
IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.
|
|
enum:
|
|
- 8
|
|
- 16
|
|
- 32
|
|
|
|
additionalProperties: true
|