139 lines
3.8 KiB
YAML
139 lines
3.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cortina Systems Gemini Ethernet Controller
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description: |
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This ethernet controller is found in the Gemini SoC family:
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StorLink SL3512 and SL3516, also known as Cortina Systems
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CS3512 and CS3516.
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properties:
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compatible:
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const: cortina,gemini-ethernet
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reg:
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minItems: 3
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description: must contain the global registers and the V-bit and A-bit
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memory areas, in total three register sets.
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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#The subnodes represents the two ethernet ports in this device.
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#They are not independent of each other since they share resources
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#in the parent node, and are thus children.
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patternProperties:
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"^ethernet-port@[0-9]+$":
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type: object
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unevaluatedProperties: false
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description: contains the resources for ethernet port
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allOf:
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- $ref: ethernet-controller.yaml#
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properties:
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compatible:
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const: cortina,gemini-ethernet-port
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reg:
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items:
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- description: DMA/TOE memory
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- description: GMAC memory area of the port
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interrupts:
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maxItems: 1
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description: should contain the interrupt line of the port.
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this is nominally a level interrupt active high.
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resets:
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maxItems: 1
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description: this must provide an SoC-integrated reset line for the port.
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clocks:
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maxItems: 1
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description: this should contain a handle to the PCLK clock for
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clocking the silicon in this port
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clock-names:
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const: PCLK
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required:
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- reg
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- compatible
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- interrupts
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- resets
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- clocks
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- clock-names
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required:
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- compatible
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- reg
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/cortina,gemini-clock.h>
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#include <dt-bindings/reset/cortina,gemini-reset.h>
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mdio0: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@1 {
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reg = <1>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@3 {
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reg = <3>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@60000000 {
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compatible = "cortina,gemini-ethernet";
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reg = <0x60000000 0x4000>, /* Global registers, queue */
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<0x60004000 0x2000>, /* V-bit */
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<0x60006000 0x2000>; /* A-bit */
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gmac0: ethernet-port@0 {
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compatible = "cortina,gemini-ethernet-port";
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reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
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<0x6000a000 0x2000>; /* Port 0 GMAC */
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interrupt-parent = <&intcon>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon GEMINI_RESET_GMAC0>;
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clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
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clock-names = "PCLK";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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gmac1: ethernet-port@1 {
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compatible = "cortina,gemini-ethernet-port";
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reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
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<0x6000e000 0x2000>; /* Port 1 GMAC */
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interrupt-parent = <&intcon>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon GEMINI_RESET_GMAC1>;
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clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
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clock-names = "PCLK";
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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};
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