264 lines
7.2 KiB
YAML
264 lines
7.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/fsl,fec.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Fast Ethernet Controller (FEC)
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maintainers:
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- Shawn Guo <shawnguo@kernel.org>
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- Wei Fang <wei.fang@nxp.com>
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- NXP Linux Team <linux-imx@nxp.com>
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allOf:
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- $ref: ethernet-controller.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,imx25-fec
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- fsl,imx27-fec
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- fsl,imx28-fec
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- fsl,imx6q-fec
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- fsl,mvf600-fec
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- fsl,s32v234-fec
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- items:
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- enum:
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- fsl,imx53-fec
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- fsl,imx6sl-fec
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- const: fsl,imx25-fec
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- items:
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- enum:
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- fsl,imx35-fec
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- fsl,imx51-fec
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- const: fsl,imx27-fec
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- items:
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- enum:
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- fsl,imx6ul-fec
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- fsl,imx6sx-fec
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- const: fsl,imx6q-fec
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- items:
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- enum:
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- fsl,imx7d-fec
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- const: fsl,imx6sx-fec
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- items:
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- const: fsl,imx8mq-fec
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- const: fsl,imx6sx-fec
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- items:
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- enum:
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- fsl,imx8mm-fec
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- fsl,imx8mn-fec
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- fsl,imx8mp-fec
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- fsl,imx93-fec
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- const: fsl,imx8mq-fec
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- const: fsl,imx6sx-fec
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- items:
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- const: fsl,imx8qm-fec
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- const: fsl,imx6sx-fec
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- items:
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- enum:
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- fsl,imx8qxp-fec
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- const: fsl,imx8qm-fec
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- const: fsl,imx6sx-fec
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- items:
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- enum:
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- fsl,imx8ulp-fec
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- const: fsl,imx6ul-fec
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- const: fsl,imx6q-fec
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 4
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interrupt-names:
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oneOf:
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- items:
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- const: int0
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- items:
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- const: int0
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- const: pps
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- items:
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- const: int0
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- const: int1
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- const: int2
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- items:
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- const: int0
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- const: int1
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- const: int2
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- const: pps
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clocks:
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minItems: 2
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maxItems: 5
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description:
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The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing.
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The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.
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The "ptp"(option), for IEEE1588 timer clock that requires the clock.
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The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
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RGMII TXC clock or RMII reference clock. It depends on board design,
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the clock is required if RGMII TXC and RMII reference clock source from
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SOC internal PLL.
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The "enet_out"(option), output clock for external device, like supply clock
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for PHY. The clock is required if PHY clock source from SOC.
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The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.
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The clock is required if SoC RGMII enable clock delay.
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clock-names:
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minItems: 2
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maxItems: 5
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items:
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enum:
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- ipg
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- ahb
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- ptp
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- enet_clk_ref
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- enet_out
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- enet_2x_txclk
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phy-mode: true
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phy-handle: true
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fixed-link: true
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local-mac-address: true
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mac-address: true
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nvmem-cells: true
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nvmem-cell-names: true
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tx-internal-delay-ps:
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enum: [0, 2000]
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rx-internal-delay-ps:
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enum: [0, 2000]
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phy-supply:
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description:
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Regulator that powers the Ethernet PHY.
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fsl,num-tx-queues:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The property is valid for enet-avb IP, which supports hw multi queues.
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Should specify the tx queue number, otherwise set tx queue number to 1.
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enum: [1, 2, 3]
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fsl,num-rx-queues:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The property is valid for enet-avb IP, which supports hw multi queues.
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Should specify the rx queue number, otherwise set rx queue number to 1.
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enum: [1, 2, 3]
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fsl,magic-packet:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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If present, indicates that the hardware supports waking up via magic packet.
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fsl,err006687-workaround-present:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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If present indicates that the system has the hardware workaround for
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ERR006687 applied and does not need a software workaround.
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fsl,stop-mode:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to general purpose register node
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- description: the gpr register offset for ENET stop request
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- description: the gpr bit offset for ENET stop request
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description:
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Register bits of stop mode control, the format is <&gpr req_gpr req_bit>.
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mdio:
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$ref: mdio.yaml#
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unevaluatedProperties: false
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description:
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Specifies the mdio bus in the FEC, used as a container for phy nodes.
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# Deprecated optional properties:
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# To avoid these, create a phy node according to ethernet-phy.yaml in the same
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# directory, and point the FEC's "phy-handle" property to it. Then use
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# the phy's reset binding, again described by ethernet-phy.yaml.
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phy-reset-gpios:
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deprecated: true
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description:
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Should specify the gpio for phy reset.
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phy-reset-duration:
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$ref: /schemas/types.yaml#/definitions/uint32
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deprecated: true
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description:
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Reset duration in milliseconds. Should present only if property
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"phy-reset-gpios" is available. Missing the property will have the
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duration be 1 millisecond. Numbers greater than 1000 are invalid
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and 1 millisecond will be used instead.
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phy-reset-active-high:
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type: boolean
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deprecated: true
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description:
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If present then the reset sequence using the GPIO specified in the
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"phy-reset-gpios" property is reversed (H=reset state, L=operation state).
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phy-reset-post-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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deprecated: true
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description:
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Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay
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milliseconds will be observed after the phy-reset-gpios has been toggled.
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Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms.
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Other delays are invalid.
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required:
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- compatible
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- reg
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- interrupts
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# FIXME: We had better set additionalProperties to false to avoid invalid or at
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# least undocumented properties. However, PHY may have a deprecated option to
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# place PHY OF properties in the MAC node, such as Micrel PHY, and we can find
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# these boards which is based on i.MX6QDL.
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unevaluatedProperties: false
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examples:
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- |
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ethernet@83fec000 {
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compatible = "fsl,imx51-fec", "fsl,imx27-fec";
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reg = <0x83fec000 0x4000>;
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interrupts = <87>;
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phy-mode = "mii";
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phy-reset-gpios = <&gpio2 14 0>;
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phy-supply = <®_fec_supply>;
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};
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ethernet@83fed000 {
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compatible = "fsl,imx51-fec", "fsl,imx27-fec";
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reg = <0x83fed000 0x4000>;
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interrupts = <87>;
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phy-mode = "mii";
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phy-reset-gpios = <&gpio2 14 0>;
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phy-supply = <®_fec_supply>;
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phy-handle = <ðphy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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};
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};
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