161 lines
7.0 KiB
YAML
161 lines
7.0 KiB
YAML
# SPDX-License-Identifier: BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V SBI PMU events
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maintainers:
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- Atish Patra <atishp@rivosinc.com>
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description: |
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The SBI PMU extension allows supervisor software to configure, start and
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stop any performance counter at anytime. Thus, a user can leverage all
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capabilities of performance analysis tools, such as perf, if the SBI PMU
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extension is enabled. The following constraints apply:
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The platform must provide information about PMU event to counter mappings
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either via device tree or another way, specific to the platform.
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Without the event to counter mappings, the SBI PMU extension cannot be used.
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Platforms should provide information about the PMU event selector values
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that should be encoded in the expected value of MHPMEVENTx while configuring
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MHPMCOUNTERx for that specific event. The can either be done via device tree
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or another way, specific to the platform.
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The exact value to be written to MHPMEVENTx is completely dependent on the
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platform.
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For information on the SBI specification see the section "Performance
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Monitoring Unit Extension" of:
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https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
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properties:
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compatible:
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const: riscv,pmu
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riscv,event-to-mhpmevent:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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description:
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Represents an ONE-to-ONE mapping between a PMU event and the event
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selector value that the platform expects to be written to the MHPMEVENTx
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CSR for that event.
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The mapping is encoded in an matrix format where each element represents
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an event.
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This property shouldn't encode any raw hardware event.
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items:
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items:
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- description: event_idx, a 20-bit wide encoding of the event type and
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code. Refer to the SBI specification for a complete description of
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the event types and codes.
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- description: upper 32 bits of the event selector value for MHPMEVENTx
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- description: lower 32 bits of the event selector value for MHPMEVENTx
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riscv,event-to-mhpmcounters:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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description:
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Represents a MANY-to-MANY mapping between a range of events and all the
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MHPMCOUNTERx in a bitmap format that can be used to monitor these range
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of events. The information is encoded in an matrix format where each
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element represents a certain range of events and corresponding counters.
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This property shouldn't encode any raw event.
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items:
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items:
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- description: first event_idx of the range of events
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- description: last event_idx of the range of events
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- description: bitmap of MHPMCOUNTERx for this event
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riscv,raw-event-to-mhpmcounters:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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description:
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Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s)
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and all the MHPMCOUNTERx in a bitmap format that can be used to monitor
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that raw event.
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The encoding of the raw events are platform specific. The information is
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encoded in a matrix format where each element represents the specific raw
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event(s).
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If a platform directly encodes each raw PMU event as a unique ID, the
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value of variant must be 0xffffffff_ffffffff.
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items:
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items:
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- description:
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upper 32 invariant bits for the range of events
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- description:
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lower 32 invariant bits for the range of events
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- description:
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upper 32 bits of the variant bit mask for the range of events
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- description:
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lower 32 bits of the variant bit mask for the range of events
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- description:
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bitmap of all MHPMCOUNTERx that can monitor the range of events
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dependencies:
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"riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ]
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required:
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- compatible
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additionalProperties: false
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examples:
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- |
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pmu {
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compatible = "riscv,pmu";
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riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
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riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
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<0x00002 0x00002 0x00000004>,
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<0x00003 0x0000A 0x00000ff8>,
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<0x10000 0x10033 0x000ff000>;
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riscv,raw-event-to-mhpmcounters =
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/* For event ID 0x0002 */
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<0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
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/* For event ID 0-4 */
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<0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
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/* For event ID 0xffffffff0000000f - 0xffffffff000000ff */
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<0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>;
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};
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- |
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/*
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* For HiFive Unmatched board the encodings can be found here
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* https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
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*
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* This example also binds standard SBI PMU hardware IDs to U74 PMU event
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* codes, U74 uses a bitfield for events encoding, so several U74 events
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* can be bound to a single perf ID.
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* See SBI PMU hardware IDs in arch/riscv/include/asm/sbi.h
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*/
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pmu {
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compatible = "riscv,pmu";
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riscv,event-to-mhpmevent =
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/* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */
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<0x00003 0x00000000 0x1801>,
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/* SBI_PMU_HW_CACHE_MISSES -> Instruction or Data cache miss or MMIO access */
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<0x00004 0x00000000 0x0302>,
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/* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
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<0x00005 0x00000000 0x4000>,
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/* SBI_PMU_HW_BRANCH_MISSES -> Branch or jump misprediction */
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<0x00006 0x00000000 0x6001>,
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/* L1D_READ_MISS -> Data cache miss or MMIO access */
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<0x10001 0x00000000 0x0202>,
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/* L1D_WRITE_ACCESS -> Data cache write-back */
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<0x10002 0x00000000 0x0402>,
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/* L1I_READ_ACCESS -> Instruction cache miss */
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<0x10009 0x00000000 0x0102>,
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/* LL_READ_MISS -> UTLB miss */
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<0x10011 0x00000000 0x2002>,
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/* DTLB_READ_MISS -> Data TLB miss */
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<0x10019 0x00000000 0x1002>,
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/* ITLB_READ_MISS-> Instruction TLB miss */
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<0x10021 0x00000000 0x0802>;
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riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>,
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<0x10001 0x10002 0x18>,
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<0x10009 0x10009 0x18>,
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<0x10011 0x10011 0x18>,
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<0x10019 0x10019 0x18>,
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<0x10021 0x10021 0x18>;
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riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>,
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<0x0 0x1 0xffffffff 0xfff800ff 0x18>,
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<0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
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};
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