84 lines
1.7 KiB
YAML
84 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner F1C100s USB PHY
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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properties:
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"#phy-cells":
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const: 1
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compatible:
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const: allwinner,suniv-f1c100s-usb-phy
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reg:
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maxItems: 1
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description: PHY Control registers
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reg-names:
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const: phy_ctrl
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clocks:
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maxItems: 1
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description: USB OTG PHY bus clock
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clock-names:
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const: usb0_phy
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resets:
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maxItems: 1
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description: USB OTG reset
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reset-names:
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const: usb0_reset
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usb0_id_det-gpios:
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maxItems: 1
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description: GPIO to the USB OTG ID pin
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usb0_vbus_det-gpios:
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maxItems: 1
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description: GPIO to the USB OTG VBUS detect pin
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usb0_vbus_power-supply:
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description: Power supply to detect the USB OTG VBUS
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usb0_vbus-supply:
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description: Regulator controlling USB OTG VBUS
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required:
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- "#phy-cells"
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- compatible
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- clocks
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- clock-names
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- reg
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- reg-names
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
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#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
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phy@1c13400 {
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compatible = "allwinner,suniv-f1c100s-usb-phy";
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reg = <0x01c13400 0x10>;
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reg-names = "phy_ctrl";
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clocks = <&ccu CLK_USB_PHY0>;
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clock-names = "usb0_phy";
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resets = <&ccu RST_USB_PHY0>;
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reset-names = "usb0_reset";
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#phy-cells = <1>;
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usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
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};
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