96 lines
2.2 KiB
YAML
96 lines
2.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Lantiq VRX200 and ARX300 PCIe PHY
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maintainers:
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- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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properties:
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"#phy-cells":
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const: 1
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description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
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compatible:
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enum:
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- lantiq,vrx200-pcie-phy
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- lantiq,arx300-pcie-phy
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reg:
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maxItems: 1
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clocks:
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items:
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- description: PHY module clock
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- description: PDI register clock
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clock-names:
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items:
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- const: phy
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- const: pdi
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resets:
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items:
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- description: exclusive PHY reset line
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- description: shared reset line between the PCIe PHY and PCIe controller
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reset-names:
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items:
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- const: phy
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- const: pcie
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lantiq,rcu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the RCU syscon
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lantiq,rcu-endian-offset:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: the offset of the endian registers for this PHY instance in the RCU syscon
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lantiq,rcu-big-endian-mask:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
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big-endian:
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description: Configures the PDI (PHY) registers in big-endian mode
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type: boolean
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little-endian:
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description: Configures the PDI (PHY) registers in big-endian mode
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type: boolean
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required:
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- "#phy-cells"
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- lantiq,rcu
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- lantiq,rcu-endian-offset
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- lantiq,rcu-big-endian-mask
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additionalProperties: false
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examples:
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- |
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pcie0_phy: phy@106800 {
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compatible = "lantiq,vrx200-pcie-phy";
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reg = <0x106800 0x100>;
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lantiq,rcu = <&rcu0>;
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lantiq,rcu-endian-offset = <0x4c>;
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lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
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big-endian;
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clocks = <&pmu 32>, <&pmu 36>;
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clock-names = "phy", "pdi";
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resets = <&reset0 12 24>, <&reset0 22 22>;
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reset-names = "phy", "pcie";
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#phy-cells = <1>;
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};
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...
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