110 lines
2.9 KiB
YAML
110 lines
2.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip SoC Naneng Combo Phy
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maintainers:
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- Heiko Stuebner <heiko@sntech.de>
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properties:
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compatible:
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enum:
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- rockchip,rk3568-naneng-combphy
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reg:
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maxItems: 1
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clocks:
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items:
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- description: reference clock
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- description: apb clock
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- description: pipe clock
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clock-names:
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items:
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- const: ref
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- const: apb
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- const: pipe
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resets:
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items:
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- description: exclusive PHY reset line
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rockchip,enable-ssc:
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type: boolean
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description:
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The option SSC can be enabled for U3, SATA and PCIE.
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Most commercially available platforms use SSC to reduce EMI.
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rockchip,ext-refclk:
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type: boolean
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description:
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Many PCIe connections, especially backplane connections,
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require a synchronous reference clock between the two link partners.
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To achieve this a common clock source, referred to as REFCLK in
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the PCI Express Card Electromechanical Specification,
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should be used by both ends of the PCIe link.
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In PCIe mode one can choose to use an internal or an external reference
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clock.
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By default the internal clock is selected. The PCIe PHY provides a 100MHz
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differential clock output(optional with SSC) for system applications.
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When selecting this option an externally 100MHz differential
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reference clock needs to be provided to the PCIe PHY.
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rockchip,pipe-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Some additional phy settings are accessed through GRF regs.
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rockchip,pipe-phy-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Some additional pipe settings are accessed through GRF regs.
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"#phy-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- rockchip,pipe-grf
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- rockchip,pipe-phy-grf
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rk3568-cru.h>
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pipegrf: syscon@fdc50000 {
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compatible = "rockchip,rk3568-pipe-grf", "syscon";
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reg = <0xfdc50000 0x1000>;
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};
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pipe_phy_grf0: syscon@fdc70000 {
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compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
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reg = <0xfdc70000 0x1000>;
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};
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combphy0: phy@fe820000 {
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compatible = "rockchip,rk3568-naneng-combphy";
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reg = <0xfe820000 0x100>;
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clocks = <&pmucru CLK_PCIEPHY0_REF>,
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<&cru PCLK_PIPEPHY0>,
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<&cru PCLK_PIPE>;
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clock-names = "ref", "apb", "pipe";
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assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
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assigned-clock-rates = <100000000>;
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resets = <&cru SRST_PIPEPHY0>;
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rockchip,pipe-grf = <&pipegrf>;
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rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
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#phy-cells = <1>;
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};
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