134 lines
4.6 KiB
YAML
134 lines
4.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. MDM9607 TLMM block
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maintainers:
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- Konrad Dybcio <konrad.dybcio@somainline.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,mdm9607-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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gpio-reserved-ranges: true
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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required:
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- compatible
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- reg
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additionalProperties: false
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-mdm9607-tlmm-state"
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- patternProperties:
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".*":
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$ref: "#/$defs/qcom-mdm9607-tlmm-state"
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$defs:
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qcom-mdm9607-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
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- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
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sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
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qdsd_data3 ]
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minItems: 1
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maxItems: 16
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
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atest_char1, atest_char2, atest_char3,
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atest_combodac_to_gpio_native, atest_gpsadc_dtest0_native,
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atest_gpsadc_dtest1_native, atest_tsens, backlight_en_b,
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bimc_dte0, bimc_dte1, blsp1_spi, blsp2_spi, blsp3_spi,
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blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
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blsp_i2c6, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4,
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blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uart3,
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blsp_uart4, blsp_uart5, blsp_uart6, blsp_uim1, blsp_uim2,
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codec_int, codec_rst, coex_uart, cri_trng, cri_trng0,
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cri_trng1, dbg_out, ebi0_wrcdc, ebi2_a, ebi2_a_d_8_b,
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ebi2_lcd, ebi2_lcd_cs_n_b, ebi2_lcd_te_b, eth_irq, eth_rst,
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gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
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gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gmac_mdio,
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gpio, gsm0_tx, lcd_rst, ldo_en, ldo_update, m_voc, modem_tsync,
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nav_ptp_pps_in_a, nav_ptp_pps_in_b, nav_tsync_out_a,
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nav_tsync_out_b, pa_indicator, pbs0, pbs1, pbs2,
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pri_mi2s_data0_a, pri_mi2s_data1_a, pri_mi2s_mclk_a,
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pri_mi2s_sck_a, pri_mi2s_ws_a, prng_rosc, ptp_pps_out_a,
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ptp_pps_out_b, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
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pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
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pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
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qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
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qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
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qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
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qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, rcm_marker1,
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rcm_marker2, sd_write, sec_mi2s, sensor_en, sensor_int2,
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sensor_int3, sensor_rst, ssbi1, ssbi2, touch_rst, ts_int,
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uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
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uim2_data, uim2_present, uim2_reset, uim_batt, wlan_en1, ]
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength: true
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input-enable: true
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output-high: true
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output-low: true
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required:
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- pins
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@1000000 {
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compatible = "qcom,mdm9607-tlmm";
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reg = <0x01000000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&msmgpio 0 0 80>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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