191 lines
6.3 KiB
YAML
191 lines
6.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sdm630-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SDM630 and SDM660 TLMM pin controller
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SDM630 and SDM660 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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enum:
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- qcom,sdm630-pinctrl
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- qcom,sdm660-pinctrl
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: south
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- const: center
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- const: north
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 57
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gpio-line-names:
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maxItems: 114
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sdm630-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sdm630-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sdm630-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$"
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- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
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sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
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atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1,
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atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
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atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20,
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atest_usb21, atest_usb22, atest_usb23, audio_ref, bimc_dte0,
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bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
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blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8_a, blsp_i2c8_b,
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blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
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blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8_a,
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blsp_spi8_b, blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1,
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blsp_uart2, blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1,
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blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async, cci_i2c,
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cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, gcc_gp1,
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gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c,
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isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync,
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mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte,
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nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0,
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phase_flag1, phase_flag10, phase_flag11, phase_flag12,
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phase_flag13, phase_flag14, phase_flag15, phase_flag16,
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phase_flag17, phase_flag18, phase_flag19, phase_flag2,
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phase_flag20, phase_flag21, phase_flag22, phase_flag23,
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phase_flag24, phase_flag25, phase_flag26, phase_flag27,
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phase_flag28, phase_flag29, phase_flag3, phase_flag30,
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phase_flag31, phase_flag4, phase_flag5, phase_flag6,
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phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, pll_reset,
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pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, pwr_modem,
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pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, qdss_cti1_b,
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qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
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qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_gpio2,
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qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
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qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request, qspi_clk,
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qspi_cs, qspi_data0, qspi_data1, qspi_data2, qspi_data3,
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qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data, sp_cmu,
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ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, uim1_clk,
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uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
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uim2_present, uim2_reset, uim_batt, vfr_1, vsense_clkout,
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vsense_data0, vsense_data1, vsense_mode, wlan1_adc0,
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wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength: true
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input-enable: true
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output-high: true
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output-low: true
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required:
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- pins
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@3100000 {
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compatible = "qcom,sdm630-pinctrl";
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reg = <0x03100000 0x400000>,
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<0x03500000 0x400000>,
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<0x03900000 0x400000>;
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reg-names = "south", "center", "north";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&tlmm 0 0 114>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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blsp1-uart1-default-state {
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pins = "gpio0", "gpio1", "gpio2", "gpio3";
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function = "gpio";
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drive-strength = <2>;
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bias-disable;
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};
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blsp2_uart1_default: blsp2-uart1-active-state {
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tx-rts-pins {
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pins = "gpio16", "gpio19";
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function = "blsp_uart5";
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drive-strength = <2>;
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bias-disable;
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};
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rx-pins {
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pins = "gpio17";
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function = "blsp_uart5";
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drive-strength = <2>;
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bias-pull-up;
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};
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cts-pins {
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pins = "gpio18";
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function = "blsp_uart5";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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};
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