153 lines
4.6 KiB
YAML
153 lines
4.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SM6125 TLMM block
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maintainers:
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- Martin Botka <martin.botka@somainline.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SM6125 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,sm6125-tlmm
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: west
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- const: south
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- const: east
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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gpio-reserved-ranges: true
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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required:
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- compatible
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- reg
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- reg-names
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additionalProperties: false
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sm6125-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sm6125-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sm6125-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$"
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- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
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atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1,
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atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2,
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atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb,
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audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
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cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng,
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cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
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ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk,
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dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
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gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en,
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ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1,
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mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte,
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nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset,
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pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable,
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qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04,
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qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx,
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swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm,
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uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
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uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger,
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wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ]
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength: true
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input-enable: true
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output-high: true
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output-low: true
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required:
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- pins
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl@500000 {
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compatible = "qcom,sm6125-tlmm";
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reg = <0x00500000 0x400000>,
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<0x00900000 0x400000>,
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<0x00d00000 0x400000>;
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reg-names = "west", "south", "east";
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&tlmm 0 0 134>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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sdc2-off-state {
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clk-pins {
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pins = "sdc2_clk";
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drive-strength = <2>;
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bias-disable;
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};
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cmd-pins {
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pins = "sdc2_cmd";
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drive-strength = <2>;
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bias-pull-up;
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};
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data-pins {
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pins = "sdc2_data";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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