378 lines
11 KiB
YAML
378 lines
11 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) Sunplus Co., Ltd.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sunplus SP7021 Pin Controller
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maintainers:
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- Dvorkin Dmitry <dvorkin@tibbo.com>
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- Wells Lu <wellslutw@gmail.com>
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description: |
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The Sunplus SP7021 pin controller is used to control SoC pins. Please
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refer to pinctrl-bindings.txt in this directory for details of the common
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pinctrl bindings used by client devices.
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SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
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are multiplexed with some special function pins. SP7021 has 3 types of
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special function pins:
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(1) function-group pins:
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Ex 1 (SPI-NOR flash):
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If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87
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will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79
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and 81 will be pins of SPI-NOR flash.
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Ex 2 (UART_0):
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If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and
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RX pins of UART_0 (UART channel 0).
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Ex 3 (eMMC):
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If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77,
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78, 79, 80, 81 will be pins of an eMMC device.
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Properties "function" and "groups" are used to select function-group
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pins.
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(2) fully pin-mux (like phone exchange mux) pins:
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GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of
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SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.)
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can be routed to any pins of fully pin-mux pins.
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Ex 1 (UART channel 1):
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If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be
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routed to GPIO 10 (3 - 1 + 8 = 10).
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If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be
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routed to GPIO 11 (4 - 1 + 8 = 11).
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If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will
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be routed to GPIO 12 (5 - 1 + 8 = 12).
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If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will
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be routed to GPIO 13 (6 - 1 + 8 = 13).
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Ex 2 (I2C channel 0):
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If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will
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be routed to GPIO 27 (20 - 1 + 8 = 27).
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If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0
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will be routed to GPIO 28 (21 - 1 + 9 = 28).
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Totally, SP7021 has 120 peripheral pins. The peripheral pins can be
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routed to any of 64 'fully pin-mux' pins.
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(3) I/O processor pins
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SP7021 has a built-in I/O processor.
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Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor.
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Vendor property "sunplus,pins" is used to select "fully pin-mux" pins,
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"I/O processor pins" and "digital GPIO" pins.
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The device node of pin controller of Sunplus SP7021 has following
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properties.
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properties:
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compatible:
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const: sunplus,sp7021-pctl
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gpio-controller: true
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'#gpio-cells':
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const: 2
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reg:
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items:
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- description: the MOON2 registers
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- description: the GPIOXT registers
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- description: the FIRST registers
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- description: the MOON1 registers
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reg-names:
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items:
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- const: moon2
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- const: gpioxt
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- const: first
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- const: moon1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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patternProperties:
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'-pins$':
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type: object
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description: |
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A pinctrl node should contain at least one subnodes representing the
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pins or function-pins group available on the machine. Each subnode
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will list the pins it needs, and how they should be configured.
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Pinctrl node's client devices use subnodes for desired pin
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configuration. Client device subnodes use below standard properties.
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$ref: pinmux-node.yaml#
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properties:
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sunplus,pins:
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description: |
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Define 'sunplus,pins' which are used by pinctrl node's client
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device.
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It consists of one or more integers which represents the config
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setting for corresponding pin. Each integer defines a individual
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pin in which:
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Bit 32~24: defines GPIO number. Its range is 0 ~ 98.
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Bit 23~16: defines types: (1) fully pin-mux pins
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(2) IO processor pins
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(3) digital GPIO pins
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Bit 15~8: defines pins of peripherals (which are defined in
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'include/dt-binging/pinctrl/sppctl.h').
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Bit 7~0: defines types or initial-state of digital GPIO pins.
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Please use macro SPPCTL_IOPAD to define the integers for pins.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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function:
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description: |
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Define pin-function which is used by pinctrl node's client device.
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The name should be one of string in the following enumeration.
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$ref: "/schemas/types.yaml#/definitions/string"
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enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD,
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UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ]
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groups:
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description: |
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Define pin-group in a specified pin-function.
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The name should be one of string in the following enumeration.
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$ref: "/schemas/types.yaml#/definitions/string"
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enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2,
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SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1,
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HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ]
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sunplus,zerofunc:
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description: |
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This is a vendor specific property. It is used to disable pins
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which are not used by pinctrl node's client device.
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Some pins may be enabled by boot-loader. We can use this
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property to disable them.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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additionalProperties: false
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allOf:
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- if:
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properties:
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function:
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enum:
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- SPI_FLASH
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then:
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properties:
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groups:
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enum:
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- SPI_FLASH1
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- SPI_FLASH2
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- if:
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properties:
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function:
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enum:
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- SPI_FLASH_4BIT
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then:
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properties:
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groups:
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enum:
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- SPI_FLASH_4BIT1
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- SPI_FLASH_4BIT2
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- if:
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properties:
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function:
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enum:
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- SPI_NAND
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then:
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properties:
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groups:
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enum:
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- SPI_NAND
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- if:
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properties:
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function:
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enum:
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- CARD0_EMMC
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then:
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properties:
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groups:
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enum:
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- CARD0_EMMC
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- if:
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properties:
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function:
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enum:
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- SD_CARD
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then:
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properties:
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groups:
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enum:
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- SD_CARD
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- if:
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properties:
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function:
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enum:
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- UA0
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then:
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properties:
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groups:
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enum:
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- UA0
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- if:
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properties:
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function:
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enum:
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- FPGA_IFX
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then:
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properties:
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groups:
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enum:
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- FPGA_IFX
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- if:
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properties:
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function:
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enum:
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- HDMI_TX
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then:
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properties:
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groups:
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enum:
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- HDMI_TX1
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- HDMI_TX2
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- HDMI_TX3
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- if:
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properties:
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function:
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enum:
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- LCDIF
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then:
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properties:
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groups:
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enum:
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- LCDIF
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- if:
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properties:
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function:
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enum:
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- USB0_OTG
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then:
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properties:
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groups:
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enum:
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- USB0_OTG
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- if:
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properties:
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function:
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enum:
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- USB1_OTG
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then:
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properties:
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groups:
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enum:
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- USB1_OTG
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required:
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- compatible
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- reg
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- reg-names
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- "#gpio-cells"
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- gpio-controller
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- clocks
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- resets
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additionalProperties: false
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allOf:
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- $ref: "pinctrl.yaml#"
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examples:
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- |
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#include <dt-bindings/pinctrl/sppctl-sp7021.h>
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pinctrl@9c000100 {
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compatible = "sunplus,sp7021-pctl";
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reg = <0x9c000100 0x100>, <0x9c000300 0x100>,
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<0x9c0032e4 0x1c>, <0x9c000080 0x20>;
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reg-names = "moon2", "gpioxt", "first", "moon1";
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&clkc 0x83>;
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resets = <&rstc 0x73>;
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uart0-pins {
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function = "UA0";
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groups = "UA0";
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};
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spinand0-pins {
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function = "SPI_NAND";
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groups = "SPI_NAND";
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};
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uart1-pins {
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sunplus,pins = <
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SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
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SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
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>;
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};
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uart2-pins {
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sunplus,pins = <
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SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
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SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
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SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0)
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SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0)
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>;
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};
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emmc-pins {
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function = "CARD0_EMMC";
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groups = "CARD0_EMMC";
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};
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sdcard-pins {
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function = "SD_CARD";
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groups = "SD_CARD";
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sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
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};
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hdmi_A_tx1-pins {
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function = "HDMI_TX";
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groups = "HDMI_TX1";
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};
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hdmi_A_tx2-pins {
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function = "HDMI_TX";
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groups = "HDMI_TX2";
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};
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hdmi_A_tx3-pins {
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function = "HDMI_TX";
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groups = "HDMI_TX3";
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};
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ethernet-pins {
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sunplus,pins = <
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SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
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SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
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SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
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SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
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SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
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SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
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SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
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SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
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SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
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>;
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sunplus,zerofunc = <
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MUXF_L2SW_LED_FLASH0
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MUXF_L2SW_LED_ON0
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MUXF_L2SW_P0_MAC_RMII_RXER
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>;
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};
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};
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...
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