116 lines
3.0 KiB
YAML
116 lines
3.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
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maintainers:
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- Heiko Stuebner <heiko@sntech.de>
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properties:
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compatible:
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const: rockchip,rk3399-dwc3
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'#address-cells':
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const: 2
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'#size-cells':
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const: 2
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ranges: true
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clocks:
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items:
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- description:
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Controller reference clock, must to be 24 MHz
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- description:
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Controller suspend clock, must to be 24 MHz or 32 KHz
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- description:
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Master/Core clock, must to be >= 62.5 MHz for SS
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operation and >= 30MHz for HS operation
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- description:
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USB3 aclk peri
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- description:
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USB3 aclk
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- description:
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Controller grf clock
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clock-names:
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items:
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- const: ref_clk
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- const: suspend_clk
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- const: bus_clk
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- const: aclk_usb3_rksoc_axi_perf
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- const: aclk_usb3
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- const: grf_clk
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resets:
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maxItems: 1
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reset-names:
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const: usb3-otg
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patternProperties:
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'^usb@':
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$ref: snps,dwc3.yaml#
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additionalProperties: false
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required:
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- compatible
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- '#address-cells'
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- '#size-cells'
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- ranges
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- clocks
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- clock-names
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- resets
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- reset-names
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examples:
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- |
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#include <dt-bindings/clock/rk3399-cru.h>
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#include <dt-bindings/power/rk3399-power.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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usb {
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compatible = "rockchip,rk3399-dwc3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
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<&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
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<&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
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clock-names = "ref_clk", "suspend_clk",
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"bus_clk", "aclk_usb3_rksoc_axi_perf",
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"aclk_usb3", "grf_clk";
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resets = <&cru SRST_A_USB3_OTG0>;
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reset-names = "usb3-otg";
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usb@fe800000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfe800000 0x0 0x100000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
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<&cru SCLK_USB3OTG0_SUSPEND>;
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clock-names = "ref", "bus_early", "suspend";
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dr_mode = "otg";
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phys = <&u2phy0_otg>, <&tcphy0_usb3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis_u2_susphy_quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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power-domains = <&power RK3399_PD_USB3>;
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};
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};
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};
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...
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