548 lines
24 KiB
ReStructuredText
548 lines
24 KiB
ReStructuredText
=====================
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PHY Abstraction Layer
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=====================
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Purpose
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=======
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Most network devices consist of set of registers which provide an interface
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to a MAC layer, which communicates with the physical connection through a
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PHY. The PHY concerns itself with negotiating link parameters with the link
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partner on the other side of the network connection (typically, an ethernet
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cable), and provides a register interface to allow drivers to determine what
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settings were chosen, and to configure what settings are allowed.
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While these devices are distinct from the network devices, and conform to a
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standard layout for the registers, it has been common practice to integrate
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the PHY management code with the network driver. This has resulted in large
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amounts of redundant code. Also, on embedded systems with multiple (and
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sometimes quite different) ethernet controllers connected to the same
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management bus, it is difficult to ensure safe use of the bus.
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Since the PHYs are devices, and the management busses through which they are
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accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
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In doing so, it has these goals:
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#. Increase code-reuse
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#. Increase overall code-maintainability
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#. Speed development time for new network drivers, and for new systems
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Basically, this layer is meant to provide an interface to PHY devices which
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allows network driver writers to write as little code as possible, while
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still providing a full feature set.
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The MDIO bus
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============
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Most network devices are connected to a PHY by means of a management bus.
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Different devices use different busses (though some share common interfaces).
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In order to take advantage of the PAL, each bus interface needs to be
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registered as a distinct device.
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#. read and write functions must be implemented. Their prototypes are::
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int write(struct mii_bus *bus, int mii_id, int regnum, u16 value);
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int read(struct mii_bus *bus, int mii_id, int regnum);
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mii_id is the address on the bus for the PHY, and regnum is the register
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number. These functions are guaranteed not to be called from interrupt
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time, so it is safe for them to block, waiting for an interrupt to signal
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the operation is complete
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#. A reset function is optional. This is used to return the bus to an
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initialized state.
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#. A probe function is needed. This function should set up anything the bus
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driver needs, setup the mii_bus structure, and register with the PAL using
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mdiobus_register. Similarly, there's a remove function to undo all of
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that (use mdiobus_unregister).
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#. Like any driver, the device_driver structure must be configured, and init
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exit functions are used to register the driver.
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#. The bus must also be declared somewhere as a device, and registered.
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As an example for how one driver implemented an mdio bus driver, see
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drivers/net/ethernet/freescale/fsl_pq_mdio.c and an associated DTS file
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for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
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(RG)MII/electrical interface considerations
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===========================================
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The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
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electrical signal interface using a synchronous 125Mhz clock signal and several
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data lines. Due to this design decision, a 1.5ns to 2ns delay must be added
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between the clock line (RXC or TXC) and the data lines to let the PHY (clock
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sink) have a large enough setup and hold time to sample the data lines correctly. The
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PHY library offers different types of PHY_INTERFACE_MODE_RGMII* values to let
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the PHY driver and optionally the MAC driver, implement the required delay. The
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values of phy_interface_t must be understood from the perspective of the PHY
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device itself, leading to the following:
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* PHY_INTERFACE_MODE_RGMII: the PHY is not responsible for inserting any
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internal delay by itself, it assumes that either the Ethernet MAC (if capable)
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or the PCB traces insert the correct 1.5-2ns delay
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* PHY_INTERFACE_MODE_RGMII_TXID: the PHY should insert an internal delay
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for the transmit data lines (TXD[3:0]) processed by the PHY device
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* PHY_INTERFACE_MODE_RGMII_RXID: the PHY should insert an internal delay
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for the receive data lines (RXD[3:0]) processed by the PHY device
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* PHY_INTERFACE_MODE_RGMII_ID: the PHY should insert internal delays for
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both transmit AND receive data lines from/to the PHY device
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Whenever possible, use the PHY side RGMII delay for these reasons:
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* PHY devices may offer sub-nanosecond granularity in how they allow a
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receiver/transmitter side delay (e.g: 0.5, 1.0, 1.5ns) to be specified. Such
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precision may be required to account for differences in PCB trace lengths
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* PHY devices are typically qualified for a large range of applications
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(industrial, medical, automotive...), and they provide a constant and
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reliable delay across temperature/pressure/voltage ranges
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* PHY device drivers in PHYLIB being reusable by nature, being able to
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configure correctly a specified delay enables more designs with similar delay
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requirements to be operated correctly
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For cases where the PHY is not capable of providing this delay, but the
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Ethernet MAC driver is capable of doing so, the correct phy_interface_t value
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should be PHY_INTERFACE_MODE_RGMII, and the Ethernet MAC driver should be
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configured correctly in order to provide the required transmit and/or receive
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side delay from the perspective of the PHY device. Conversely, if the Ethernet
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MAC driver looks at the phy_interface_t value, for any other mode but
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PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
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disabled.
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In case neither the Ethernet MAC, nor the PHY are capable of providing the
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required delays, as defined per the RGMII standard, several options may be
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available:
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* Some SoCs may offer a pin pad/mux/controller capable of configuring a given
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set of pins' strength, delays, and voltage; and it may be a suitable
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option to insert the expected 2ns RGMII delay.
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* Modifying the PCB design to include a fixed delay (e.g: using a specifically
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designed serpentine), which may not require software configuration at all.
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Common problems with RGMII delay mismatch
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-----------------------------------------
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When there is a RGMII delay mismatch between the Ethernet MAC and the PHY, this
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will most likely result in the clock and data line signals to be unstable when
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the PHY or MAC take a snapshot of these signals to translate them into logical
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1 or 0 states and reconstruct the data being transmitted/received. Typical
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symptoms include:
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* Transmission/reception partially works, and there is frequent or occasional
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packet loss observed
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* Ethernet MAC may report some or all packets ingressing with a FCS/CRC error,
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or just discard them all
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* Switching to lower speeds such as 10/100Mbits/sec makes the problem go away
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(since there is enough setup/hold time in that case)
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Connecting to a PHY
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===================
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Sometime during startup, the network driver needs to establish a connection
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between the PHY device, and the network device. At this time, the PHY's bus
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and drivers need to all have been loaded, so it is ready for the connection.
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At this point, there are several ways to connect to the PHY:
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#. The PAL handles everything, and only calls the network driver when
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the link state changes, so it can react.
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#. The PAL handles everything except interrupts (usually because the
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controller has the interrupt registers).
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#. The PAL handles everything, but checks in with the driver every second,
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allowing the network driver to react first to any changes before the PAL
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does.
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#. The PAL serves only as a library of functions, with the network device
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manually calling functions to update status, and configure the PHY
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Letting the PHY Abstraction Layer do Everything
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===============================================
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If you choose option 1 (The hope is that every driver can, but to still be
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useful to drivers that can't), connecting to the PHY is simple:
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First, you need a function to react to changes in the link state. This
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function follows this protocol::
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static void adjust_link(struct net_device *dev);
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Next, you need to know the device name of the PHY connected to this device.
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The name will look something like, "0:00", where the first number is the
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bus id, and the second is the PHY's address on that bus. Typically,
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the bus is responsible for making its ID unique.
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Now, to connect, just call this function::
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phydev = phy_connect(dev, phy_name, &adjust_link, interface);
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*phydev* is a pointer to the phy_device structure which represents the PHY.
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If phy_connect is successful, it will return the pointer. dev, here, is the
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pointer to your net_device. Once done, this function will have started the
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PHY's software state machine, and registered for the PHY's interrupt, if it
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has one. The phydev structure will be populated with information about the
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current state, though the PHY will not yet be truly operational at this
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point.
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PHY-specific flags should be set in phydev->dev_flags prior to the call
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to phy_connect() such that the underlying PHY driver can check for flags
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and perform specific operations based on them.
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This is useful if the system has put hardware restrictions on
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the PHY/controller, of which the PHY needs to be aware.
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*interface* is a u32 which specifies the connection type used
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between the controller and the PHY. Examples are GMII, MII,
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RGMII, and SGMII. See "PHY interface mode" below. For a full
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list, see include/linux/phy.h
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Now just make sure that phydev->supported and phydev->advertising have any
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values pruned from them which don't make sense for your controller (a 10/100
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controller may be connected to a gigabit capable PHY, so you would need to
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mask off SUPPORTED_1000baseT*). See include/linux/ethtool.h for definitions
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for these bitfields. Note that you should not SET any bits, except the
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SUPPORTED_Pause and SUPPORTED_AsymPause bits (see below), or the PHY may get
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put into an unsupported state.
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Lastly, once the controller is ready to handle network traffic, you call
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phy_start(phydev). This tells the PAL that you are ready, and configures the
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PHY to connect to the network. If the MAC interrupt of your network driver
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also handles PHY status changes, just set phydev->irq to PHY_MAC_INTERRUPT
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before you call phy_start and use phy_mac_interrupt() from the network
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driver. If you don't want to use interrupts, set phydev->irq to PHY_POLL.
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phy_start() enables the PHY interrupts (if applicable) and starts the
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phylib state machine.
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When you want to disconnect from the network (even if just briefly), you call
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phy_stop(phydev). This function also stops the phylib state machine and
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disables PHY interrupts.
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PHY interface modes
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===================
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The PHY interface mode supplied in the phy_connect() family of functions
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defines the initial operating mode of the PHY interface. This is not
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guaranteed to remain constant; there are PHYs which dynamically change
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their interface mode without software interaction depending on the
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negotiation results.
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Some of the interface modes are described below:
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``PHY_INTERFACE_MODE_SMII``
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This is serial MII, clocked at 125MHz, supporting 100M and 10M speeds.
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Some details can be found in
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https://opencores.org/ocsvn/smii/smii/trunk/doc/SMII.pdf
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``PHY_INTERFACE_MODE_1000BASEX``
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This defines the 1000BASE-X single-lane serdes link as defined by the
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802.3 standard section 36. The link operates at a fixed bit rate of
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1.25Gbaud using a 10B/8B encoding scheme, resulting in an underlying
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data rate of 1Gbps. Embedded in the data stream is a 16-bit control
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word which is used to negotiate the duplex and pause modes with the
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remote end. This does not include "up-clocked" variants such as 2.5Gbps
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speeds (see below.)
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``PHY_INTERFACE_MODE_2500BASEX``
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This defines a variant of 1000BASE-X which is clocked 2.5 times as fast
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as the 802.3 standard, giving a fixed bit rate of 3.125Gbaud.
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``PHY_INTERFACE_MODE_SGMII``
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This is used for Cisco SGMII, which is a modification of 1000BASE-X
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as defined by the 802.3 standard. The SGMII link consists of a single
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serdes lane running at a fixed bit rate of 1.25Gbaud with 10B/8B
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encoding. The underlying data rate is 1Gbps, with the slower speeds of
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100Mbps and 10Mbps being achieved through replication of each data symbol.
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The 802.3 control word is re-purposed to send the negotiated speed and
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duplex information from to the MAC, and for the MAC to acknowledge
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receipt. This does not include "up-clocked" variants such as 2.5Gbps
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speeds.
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Note: mismatched SGMII vs 1000BASE-X configuration on a link can
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successfully pass data in some circumstances, but the 16-bit control
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word will not be correctly interpreted, which may cause mismatches in
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duplex, pause or other settings. This is dependent on the MAC and/or
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PHY behaviour.
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``PHY_INTERFACE_MODE_5GBASER``
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This is the IEEE 802.3 Clause 129 defined 5GBASE-R protocol. It is
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identical to the 10GBASE-R protocol defined in Clause 49, with the
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exception that it operates at half the frequency. Please refer to the
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IEEE standard for the definition.
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``PHY_INTERFACE_MODE_10GBASER``
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This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol used with
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various different mediums. Please refer to the IEEE standard for a
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definition of this.
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Note: 10GBASE-R is just one protocol that can be used with XFI and SFI.
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XFI and SFI permit multiple protocols over a single SERDES lane, and
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also defines the electrical characteristics of the signals with a host
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compliance board plugged into the host XFP/SFP connector. Therefore,
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XFI and SFI are not PHY interface types in their own right.
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``PHY_INTERFACE_MODE_10GKR``
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This is the IEEE 802.3 Clause 49 defined 10GBASE-R with Clause 73
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autonegotiation. Please refer to the IEEE standard for further
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information.
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Note: due to legacy usage, some 10GBASE-R usage incorrectly makes
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use of this definition.
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``PHY_INTERFACE_MODE_25GBASER``
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This is the IEEE 802.3 PCS Clause 107 defined 25GBASE-R protocol.
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The PCS is identical to 10GBASE-R, i.e. 64B/66B encoded
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running 2.5 as fast, giving a fixed bit rate of 25.78125 Gbaud.
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Please refer to the IEEE standard for further information.
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``PHY_INTERFACE_MODE_100BASEX``
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This defines IEEE 802.3 Clause 24. The link operates at a fixed data
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rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying
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data rate of 100Mpbs.
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``PHY_INTERFACE_MODE_QUSGMII``
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This defines the Cisco the Quad USGMII mode, which is the Quad variant of
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the USGMII (Universal SGMII) link. It's very similar to QSGMII, but uses
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a Packet Control Header (PCH) instead of the 7 bytes preamble to carry not
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only the port id, but also so-called "extensions". The only documented
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extension so-far in the specification is the inclusion of timestamps, for
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PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the
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same capabilities in terms of link speed and negotiation.
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``PHY_INTERFACE_MODE_1000BASEKX``
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This is 1000BASE-X as defined by IEEE 802.3 Clause 36 with Clause 73
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autonegotiation. Generally, it will be used with a Clause 70 PMD. To
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contrast with the 1000BASE-X phy mode used for Clause 38 and 39 PMDs, this
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interface mode has different autonegotiation and only supports full duplex.
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Pause frames / flow control
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===========================
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The PHY does not participate directly in flow control/pause frames except by
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making sure that the SUPPORTED_Pause and SUPPORTED_AsymPause bits are set in
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MII_ADVERTISE to indicate towards the link partner that the Ethernet MAC
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controller supports such a thing. Since flow control/pause frames generation
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involves the Ethernet MAC driver, it is recommended that this driver takes care
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of properly indicating advertisement and support for such features by setting
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the SUPPORTED_Pause and SUPPORTED_AsymPause bits accordingly. This can be done
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either before or after phy_connect() and/or as a result of implementing the
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ethtool::set_pauseparam feature.
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Keeping Close Tabs on the PAL
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=============================
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It is possible that the PAL's built-in state machine needs a little help to
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keep your network device and the PHY properly in sync. If so, you can
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register a helper function when connecting to the PHY, which will be called
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every second before the state machine reacts to any changes. To do this, you
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need to manually call phy_attach() and phy_prepare_link(), and then call
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phy_start_machine() with the second argument set to point to your special
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handler.
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Currently there are no examples of how to use this functionality, and testing
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on it has been limited because the author does not have any drivers which use
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it (they all use option 1). So Caveat Emptor.
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Doing it all yourself
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=====================
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There's a remote chance that the PAL's built-in state machine cannot track
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the complex interactions between the PHY and your network device. If this is
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so, you can simply call phy_attach(), and not call phy_start_machine or
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phy_prepare_link(). This will mean that phydev->state is entirely yours to
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handle (phy_start and phy_stop toggle between some of the states, so you
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might need to avoid them).
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An effort has been made to make sure that useful functionality can be
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accessed without the state-machine running, and most of these functions are
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descended from functions which did not interact with a complex state-machine.
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However, again, no effort has been made so far to test running without the
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state machine, so tryer beware.
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Here is a brief rundown of the functions::
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int phy_read(struct phy_device *phydev, u16 regnum);
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int phy_write(struct phy_device *phydev, u16 regnum, u16 val);
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Simple read/write primitives. They invoke the bus's read/write function
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pointers.
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::
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void phy_print_status(struct phy_device *phydev);
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A convenience function to print out the PHY status neatly.
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::
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void phy_request_interrupt(struct phy_device *phydev);
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Requests the IRQ for the PHY interrupts.
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::
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struct phy_device * phy_attach(struct net_device *dev, const char *phy_id,
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phy_interface_t interface);
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Attaches a network device to a particular PHY, binding the PHY to a generic
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driver if none was found during bus initialization.
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::
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int phy_start_aneg(struct phy_device *phydev);
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Using variables inside the phydev structure, either configures advertising
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and resets autonegotiation, or disables autonegotiation, and configures
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forced settings.
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::
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static inline int phy_read_status(struct phy_device *phydev);
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Fills the phydev structure with up-to-date information about the current
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settings in the PHY.
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::
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int phy_ethtool_ksettings_set(struct phy_device *phydev,
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const struct ethtool_link_ksettings *cmd);
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Ethtool convenience functions.
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::
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int phy_mii_ioctl(struct phy_device *phydev,
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struct mii_ioctl_data *mii_data, int cmd);
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The MII ioctl. Note that this function will completely screw up the state
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machine if you write registers like BMCR, BMSR, ADVERTISE, etc. Best to
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use this only to write registers which are not standard, and don't set off
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a renegotiation.
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PHY Device Drivers
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==================
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With the PHY Abstraction Layer, adding support for new PHYs is
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quite easy. In some cases, no work is required at all! However,
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many PHYs require a little hand-holding to get up-and-running.
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Generic PHY driver
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------------------
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If the desired PHY doesn't have any errata, quirks, or special
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features you want to support, then it may be best to not add
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support, and let the PHY Abstraction Layer's Generic PHY Driver
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do all of the work.
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Writing a PHY driver
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--------------------
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If you do need to write a PHY driver, the first thing to do is
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make sure it can be matched with an appropriate PHY device.
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This is done during bus initialization by reading the device's
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UID (stored in registers 2 and 3), then comparing it to each
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driver's phy_id field by ANDing it with each driver's
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phy_id_mask field. Also, it needs a name. Here's an example::
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static struct phy_driver dm9161_driver = {
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.phy_id = 0x0181b880,
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.name = "Davicom DM9161E",
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.phy_id_mask = 0x0ffffff0,
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...
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}
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Next, you need to specify what features (speed, duplex, autoneg,
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etc) your PHY device and driver support. Most PHYs support
|
|
PHY_BASIC_FEATURES, but you can look in include/mii.h for other
|
|
features.
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|
|
|
Each driver consists of a number of function pointers, documented
|
|
in include/linux/phy.h under the phy_driver structure.
|
|
|
|
Of these, only config_aneg and read_status are required to be
|
|
assigned by the driver code. The rest are optional. Also, it is
|
|
preferred to use the generic phy driver's versions of these two
|
|
functions if at all possible: genphy_read_status and
|
|
genphy_config_aneg. If this is not possible, it is likely that
|
|
you only need to perform some actions before and after invoking
|
|
these functions, and so your functions will wrap the generic
|
|
ones.
|
|
|
|
Feel free to look at the Marvell, Cicada, and Davicom drivers in
|
|
drivers/net/phy/ for examples (the lxt and qsemi drivers have
|
|
not been tested as of this writing).
|
|
|
|
The PHY's MMD register accesses are handled by the PAL framework
|
|
by default, but can be overridden by a specific PHY driver if
|
|
required. This could be the case if a PHY was released for
|
|
manufacturing before the MMD PHY register definitions were
|
|
standardized by the IEEE. Most modern PHYs will be able to use
|
|
the generic PAL framework for accessing the PHY's MMD registers.
|
|
An example of such usage is for Energy Efficient Ethernet support,
|
|
implemented in the PAL. This support uses the PAL to access MMD
|
|
registers for EEE query and configuration if the PHY supports
|
|
the IEEE standard access mechanisms, or can use the PHY's specific
|
|
access interfaces if overridden by the specific PHY driver. See
|
|
the Micrel driver in drivers/net/phy/ for an example of how this
|
|
can be implemented.
|
|
|
|
Board Fixups
|
|
============
|
|
|
|
Sometimes the specific interaction between the platform and the PHY requires
|
|
special handling. For instance, to change where the PHY's clock input is,
|
|
or to add a delay to account for latency issues in the data path. In order
|
|
to support such contingencies, the PHY Layer allows platform code to register
|
|
fixups to be run when the PHY is brought up (or subsequently reset).
|
|
|
|
When the PHY Layer brings up a PHY it checks to see if there are any fixups
|
|
registered for it, matching based on UID (contained in the PHY device's phy_id
|
|
field) and the bus identifier (contained in phydev->dev.bus_id). Both must
|
|
match, however two constants, PHY_ANY_ID and PHY_ANY_UID, are provided as
|
|
wildcards for the bus ID and UID, respectively.
|
|
|
|
When a match is found, the PHY layer will invoke the run function associated
|
|
with the fixup. This function is passed a pointer to the phy_device of
|
|
interest. It should therefore only operate on that PHY.
|
|
|
|
The platform code can either register the fixup using phy_register_fixup()::
|
|
|
|
int phy_register_fixup(const char *phy_id,
|
|
u32 phy_uid, u32 phy_uid_mask,
|
|
int (*run)(struct phy_device *));
|
|
|
|
Or using one of the two stubs, phy_register_fixup_for_uid() and
|
|
phy_register_fixup_for_id()::
|
|
|
|
int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
|
|
int (*run)(struct phy_device *));
|
|
int phy_register_fixup_for_id(const char *phy_id,
|
|
int (*run)(struct phy_device *));
|
|
|
|
The stubs set one of the two matching criteria, and set the other one to
|
|
match anything.
|
|
|
|
When phy_register_fixup() or \*_for_uid()/\*_for_id() is called at module load
|
|
time, the module needs to unregister the fixup and free allocated memory when
|
|
it's unloaded.
|
|
|
|
Call one of following function before unloading module::
|
|
|
|
int phy_unregister_fixup(const char *phy_id, u32 phy_uid, u32 phy_uid_mask);
|
|
int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask);
|
|
int phy_register_fixup_for_id(const char *phy_id);
|
|
|
|
Standards
|
|
=========
|
|
|
|
IEEE Standard 802.3: CSMA/CD Access Method and Physical Layer Specifications, Section Two:
|
|
http://standards.ieee.org/getieee802/download/802.3-2008_section2.pdf
|
|
|
|
RGMII v1.3:
|
|
http://web.archive.org/web/20160303212629/http://www.hp.com/rnd/pdfs/RGMIIv1_3.pdf
|
|
|
|
RGMII v2.0:
|
|
http://web.archive.org/web/20160303171328/http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf
|