518 lines
16 KiB
C
518 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ALPHA_CIA__H__
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#define __ALPHA_CIA__H__
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/* Define to experiment with fitting everything into one 512MB HAE window. */
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#define CIA_ONE_HAE_WINDOW 1
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#include <linux/types.h>
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#include <asm/compiler.h>
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/*
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* CIA is the internal name for the 21171 chipset which provides
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* memory controller and PCI access for the 21164 chip based systems.
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* Also supported here is the 21172 (CIA-2) and 21174 (PYXIS).
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*
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* The lineage is a bit confused, since the 21174 was reportedly started
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* from the 21171 Pass 1 mask, and so is missing bug fixes that appear
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* in 21171 Pass 2 and 21172, but it also contains additional features.
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*
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* This file is based on:
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*
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* DECchip 21171 Core Logic Chipset
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* Technical Reference Manual
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*
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* EC-QE18B-TE
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*
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* david.rusling@reo.mts.dec.com Initial Version.
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*
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*/
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/*
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* CIA ADDRESS BIT DEFINITIONS
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*
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* 3333 3333 3322 2222 2222 1111 1111 11
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* 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
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* ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
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* 1 000
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* ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
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* | |\|
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* | Byte Enable --+ |
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* | Transfer Length --+
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* +-- IO space, not cached
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*
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* Byte Transfer
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* Enable Length Transfer Byte Address
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* adr<6:5> adr<4:3> Length Enable Adder
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* ---------------------------------------------
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* 00 00 Byte 1110 0x000
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* 01 00 Byte 1101 0x020
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* 10 00 Byte 1011 0x040
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* 11 00 Byte 0111 0x060
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*
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* 00 01 Word 1100 0x008
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* 01 01 Word 1001 0x028 <= Not supported in this code.
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* 10 01 Word 0011 0x048
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*
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* 00 10 Tribyte 1000 0x010
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* 01 10 Tribyte 0001 0x030
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*
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* 10 11 Longword 0000 0x058
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*
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* Note that byte enables are asserted low.
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*
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*/
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#define CIA_MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */
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#define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */
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#define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
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/*
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* 21171-CA Control and Status Registers
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*/
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#define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
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# define CIA_REV_MASK 0xff
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#define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
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#define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
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# define CIA_CTRL_PCI_EN (1 << 0)
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# define CIA_CTRL_PCI_LOCK_EN (1 << 1)
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# define CIA_CTRL_PCI_LOOP_EN (1 << 2)
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# define CIA_CTRL_FST_BB_EN (1 << 3)
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# define CIA_CTRL_PCI_MST_EN (1 << 4)
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# define CIA_CTRL_PCI_MEM_EN (1 << 5)
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# define CIA_CTRL_PCI_REQ64_EN (1 << 6)
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# define CIA_CTRL_PCI_ACK64_EN (1 << 7)
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# define CIA_CTRL_ADDR_PE_EN (1 << 8)
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# define CIA_CTRL_PERR_EN (1 << 9)
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# define CIA_CTRL_FILL_ERR_EN (1 << 10)
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# define CIA_CTRL_MCHK_ERR_EN (1 << 11)
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# define CIA_CTRL_ECC_CHK_EN (1 << 12)
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# define CIA_CTRL_ASSERT_IDLE_BC (1 << 13)
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# define CIA_CTRL_COM_IDLE_BC (1 << 14)
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# define CIA_CTRL_CSR_IOA_BYPASS (1 << 15)
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# define CIA_CTRL_IO_FLUSHREQ_EN (1 << 16)
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# define CIA_CTRL_CPU_FLUSHREQ_EN (1 << 17)
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# define CIA_CTRL_ARB_CPU_EN (1 << 18)
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# define CIA_CTRL_EN_ARB_LINK (1 << 19)
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# define CIA_CTRL_RD_TYPE_SHIFT 20
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# define CIA_CTRL_RL_TYPE_SHIFT 24
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# define CIA_CTRL_RM_TYPE_SHIFT 28
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# define CIA_CTRL_EN_DMA_RD_PERF (1 << 31)
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#define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
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# define CIA_CNFG_IOA_BWEN (1 << 0)
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# define CIA_CNFG_PCI_MWEN (1 << 4)
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# define CIA_CNFG_PCI_DWEN (1 << 5)
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# define CIA_CNFG_PCI_WLEN (1 << 8)
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#define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL)
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#define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
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#define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
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#define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
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#define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
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# define CIA_CACK_EN_LOCK_EN (1 << 0)
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# define CIA_CACK_EN_MB_EN (1 << 1)
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# define CIA_CACK_EN_SET_DIRTY_EN (1 << 2)
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# define CIA_CACK_EN_BC_VICTIM_EN (1 << 3)
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/*
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* 21171-CA Diagnostic Registers
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*/
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#define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)
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#define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL)
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/*
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* 21171-CA Performance Monitor registers
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*/
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#define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL)
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#define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL)
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/*
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* 21171-CA Error registers
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*/
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#define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL)
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#define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL)
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#define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL)
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# define CIA_ERR_COR_ERR (1 << 0)
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# define CIA_ERR_UN_COR_ERR (1 << 1)
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# define CIA_ERR_CPU_PE (1 << 2)
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# define CIA_ERR_MEM_NEM (1 << 3)
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# define CIA_ERR_PCI_SERR (1 << 4)
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# define CIA_ERR_PERR (1 << 5)
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# define CIA_ERR_PCI_ADDR_PE (1 << 6)
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# define CIA_ERR_RCVD_MAS_ABT (1 << 7)
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# define CIA_ERR_RCVD_TAR_ABT (1 << 8)
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# define CIA_ERR_PA_PTE_INV (1 << 9)
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# define CIA_ERR_FROM_WRT_ERR (1 << 10)
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# define CIA_ERR_IOA_TIMEOUT (1 << 11)
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# define CIA_ERR_LOST_CORR_ERR (1 << 16)
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# define CIA_ERR_LOST_UN_CORR_ERR (1 << 17)
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# define CIA_ERR_LOST_CPU_PE (1 << 18)
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# define CIA_ERR_LOST_MEM_NEM (1 << 19)
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# define CIA_ERR_LOST_PERR (1 << 21)
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# define CIA_ERR_LOST_PCI_ADDR_PE (1 << 22)
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# define CIA_ERR_LOST_RCVD_MAS_ABT (1 << 23)
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# define CIA_ERR_LOST_RCVD_TAR_ABT (1 << 24)
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# define CIA_ERR_LOST_PA_PTE_INV (1 << 25)
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# define CIA_ERR_LOST_FROM_WRT_ERR (1 << 26)
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# define CIA_ERR_LOST_IOA_TIMEOUT (1 << 27)
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# define CIA_ERR_VALID (1 << 31)
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#define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL)
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#define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL)
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#define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL)
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#define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL)
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#define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL)
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#define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL)
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#define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL)
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#define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL)
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/*
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* 21171-CA System configuration registers
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*/
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#define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL)
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#define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL)
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#define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL)
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#define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL)
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#define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL)
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#define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL)
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#define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL)
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#define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL)
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#define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL)
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#define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL)
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#define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL)
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#define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL)
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/*
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* 2117A-CA PCI Address and Scatter-Gather Registers.
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*/
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#define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL)
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#define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL)
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#define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL)
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#define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
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#define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
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#define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)
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#define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)
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#define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)
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#define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)
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#define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)
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#define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)
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#define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)
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#define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)
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#define CIA_IOC_PCI_Wn_BASE(N) (IDENT_ADDR + 0x8760000400UL + (N)*0x100)
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#define CIA_IOC_PCI_Wn_MASK(N) (IDENT_ADDR + 0x8760000440UL + (N)*0x100)
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#define CIA_IOC_PCI_Tn_BASE(N) (IDENT_ADDR + 0x8760000480UL + (N)*0x100)
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#define CIA_IOC_PCI_W_DAC (IDENT_ADDR + 0x87600007C0UL)
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/*
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* 2117A-CA Address Translation Registers.
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*/
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/* 8 tag registers, the first 4 of which are lockable. */
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#define CIA_IOC_TB_TAGn(n) \
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(IDENT_ADDR + 0x8760000800UL + (n)*0x40)
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/* 4 page registers per tag register. */
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#define CIA_IOC_TBn_PAGEm(n,m) \
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(IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
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/*
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* Memory spaces:
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*/
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#define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)
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#define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
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#define CIA_IO (IDENT_ADDR + 0x8580000000UL)
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#define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL)
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#define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL)
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#define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL)
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#define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL)
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#define CIA_BW_MEM (IDENT_ADDR + 0x8800000000UL)
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#define CIA_BW_IO (IDENT_ADDR + 0x8900000000UL)
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#define CIA_BW_CFG_0 (IDENT_ADDR + 0x8a00000000UL)
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#define CIA_BW_CFG_1 (IDENT_ADDR + 0x8b00000000UL)
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/*
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* ALCOR's GRU ASIC registers
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*/
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#define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL)
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#define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL)
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#define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL)
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#define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL)
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#define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL)
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#define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL)
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#define GRU_SCR (IDENT_ADDR + 0x8780000300UL)
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#define GRU_LED (IDENT_ADDR + 0x8780000800UL)
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#define GRU_RESET (IDENT_ADDR + 0x8780000900UL)
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#define ALCOR_GRU_INT_REQ_BITS 0x800fffffUL
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#define XLT_GRU_INT_REQ_BITS 0x80003fffUL
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#define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0)
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/*
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* PYXIS interrupt control registers
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*/
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#define PYXIS_INT_REQ (IDENT_ADDR + 0x87A0000000UL)
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#define PYXIS_INT_MASK (IDENT_ADDR + 0x87A0000040UL)
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#define PYXIS_INT_HILO (IDENT_ADDR + 0x87A00000C0UL)
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#define PYXIS_INT_ROUTE (IDENT_ADDR + 0x87A0000140UL)
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#define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL)
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#define PYXIS_INT_CNFG (IDENT_ADDR + 0x87A00001C0UL)
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#define PYXIS_RT_COUNT (IDENT_ADDR + 0x87A0000200UL)
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#define PYXIS_INT_TIME (IDENT_ADDR + 0x87A0000240UL)
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#define PYXIS_IIC_CTRL (IDENT_ADDR + 0x87A00002C0UL)
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#define PYXIS_RESET (IDENT_ADDR + 0x8780000900UL)
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/* Offset between ram physical addresses and pci64 DAC bus addresses. */
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#define PYXIS_DAC_OFFSET (1UL << 40)
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/*
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* Data structure for handling CIA machine checks.
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*/
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/* System-specific info. */
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struct el_CIA_sysdata_mcheck {
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unsigned long cpu_err0;
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unsigned long cpu_err1;
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unsigned long cia_err;
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unsigned long cia_stat;
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unsigned long err_mask;
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unsigned long cia_syn;
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unsigned long mem_err0;
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unsigned long mem_err1;
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unsigned long pci_err0;
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unsigned long pci_err1;
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unsigned long pci_err2;
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};
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#ifdef __KERNEL__
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#ifndef __EXTERN_INLINE
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/* Do not touch, this should *NOT* be static inline */
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#define __EXTERN_INLINE extern inline
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#define __IO_EXTERN_INLINE
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#endif
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/*
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* I/O functions:
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*
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* CIA (the 2117x PCI/memory support chipset for the EV5 (21164)
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* series of processors uses a sparse address mapping scheme to
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* get at PCI memory and I/O.
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*/
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/*
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* Memory functions. 64-bit and 32-bit accesses are done through
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* dense memory space, everything else through sparse space.
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*
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* For reading and writing 8 and 16 bit quantities we need to
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* go through one of the three sparse address mapping regions
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* and use the HAE_MEM CSR to provide some bits of the address.
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* The following few routines use only sparse address region 1
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* which gives 1Gbyte of accessible space which relates exactly
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* to the amount of PCI memory mapping *into* system address space.
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* See p 6-17 of the specification but it looks something like this:
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*
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* 21164 Address:
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*
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* 3 2 1
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* 9876543210987654321098765432109876543210
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* 1ZZZZ0.PCI.QW.Address............BBLL
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*
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* ZZ = SBZ
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* BB = Byte offset
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* LL = Transfer length
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*
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* PCI Address:
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*
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* 3 2 1
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* 10987654321098765432109876543210
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* HHH....PCI.QW.Address........ 00
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*
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* HHH = 31:29 HAE_MEM CSR
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*
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*/
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#define vip volatile int __force *
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#define vuip volatile unsigned int __force *
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#define vulp volatile unsigned long __force *
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__EXTERN_INLINE u8 cia_ioread8(const void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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unsigned long result, base_and_type;
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if (addr >= CIA_DENSE_MEM)
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base_and_type = CIA_SPARSE_MEM + 0x00;
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else
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base_and_type = CIA_IO + 0x00;
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/* We can use CIA_MEM_R1_MASK for io ports too, since it is large
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enough to cover all io ports, and smaller than CIA_IO. */
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addr &= CIA_MEM_R1_MASK;
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result = *(vip) ((addr << 5) + base_and_type);
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return __kernel_extbl(result, addr & 3);
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}
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__EXTERN_INLINE void cia_iowrite8(u8 b, void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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unsigned long w, base_and_type;
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if (addr >= CIA_DENSE_MEM)
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base_and_type = CIA_SPARSE_MEM + 0x00;
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else
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base_and_type = CIA_IO + 0x00;
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addr &= CIA_MEM_R1_MASK;
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w = __kernel_insbl(b, addr & 3);
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*(vuip) ((addr << 5) + base_and_type) = w;
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}
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__EXTERN_INLINE u16 cia_ioread16(const void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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unsigned long result, base_and_type;
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if (addr >= CIA_DENSE_MEM)
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base_and_type = CIA_SPARSE_MEM + 0x08;
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else
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base_and_type = CIA_IO + 0x08;
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addr &= CIA_MEM_R1_MASK;
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result = *(vip) ((addr << 5) + base_and_type);
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return __kernel_extwl(result, addr & 3);
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}
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__EXTERN_INLINE void cia_iowrite16(u16 b, void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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unsigned long w, base_and_type;
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if (addr >= CIA_DENSE_MEM)
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base_and_type = CIA_SPARSE_MEM + 0x08;
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else
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base_and_type = CIA_IO + 0x08;
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addr &= CIA_MEM_R1_MASK;
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w = __kernel_inswl(b, addr & 3);
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*(vuip) ((addr << 5) + base_and_type) = w;
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}
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__EXTERN_INLINE u32 cia_ioread32(const void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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if (addr < CIA_DENSE_MEM)
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addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
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return *(vuip)addr;
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}
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__EXTERN_INLINE void cia_iowrite32(u32 b, void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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if (addr < CIA_DENSE_MEM)
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|
addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
|
|
*(vuip)addr = b;
|
|
}
|
|
|
|
__EXTERN_INLINE u64 cia_ioread64(const void __iomem *xaddr)
|
|
{
|
|
unsigned long addr = (unsigned long) xaddr;
|
|
if (addr < CIA_DENSE_MEM)
|
|
addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
|
|
return *(vulp)addr;
|
|
}
|
|
|
|
__EXTERN_INLINE void cia_iowrite64(u64 b, void __iomem *xaddr)
|
|
{
|
|
unsigned long addr = (unsigned long) xaddr;
|
|
if (addr < CIA_DENSE_MEM)
|
|
addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
|
|
*(vulp)addr = b;
|
|
}
|
|
|
|
__EXTERN_INLINE void __iomem *cia_ioportmap(unsigned long addr)
|
|
{
|
|
return (void __iomem *)(addr + CIA_IO);
|
|
}
|
|
|
|
__EXTERN_INLINE void __iomem *cia_ioremap(unsigned long addr,
|
|
unsigned long size)
|
|
{
|
|
return (void __iomem *)(addr + CIA_DENSE_MEM);
|
|
}
|
|
|
|
__EXTERN_INLINE int cia_is_ioaddr(unsigned long addr)
|
|
{
|
|
return addr >= IDENT_ADDR + 0x8000000000UL;
|
|
}
|
|
|
|
__EXTERN_INLINE int cia_is_mmio(const volatile void __iomem *addr)
|
|
{
|
|
return (unsigned long)addr >= CIA_DENSE_MEM;
|
|
}
|
|
|
|
__EXTERN_INLINE void __iomem *cia_bwx_ioportmap(unsigned long addr)
|
|
{
|
|
return (void __iomem *)(addr + CIA_BW_IO);
|
|
}
|
|
|
|
__EXTERN_INLINE void __iomem *cia_bwx_ioremap(unsigned long addr,
|
|
unsigned long size)
|
|
{
|
|
return (void __iomem *)(addr + CIA_BW_MEM);
|
|
}
|
|
|
|
__EXTERN_INLINE int cia_bwx_is_ioaddr(unsigned long addr)
|
|
{
|
|
return addr >= IDENT_ADDR + 0x8000000000UL;
|
|
}
|
|
|
|
__EXTERN_INLINE int cia_bwx_is_mmio(const volatile void __iomem *addr)
|
|
{
|
|
return (unsigned long)addr < CIA_BW_IO;
|
|
}
|
|
|
|
#undef vip
|
|
#undef vuip
|
|
#undef vulp
|
|
|
|
#undef __IO_PREFIX
|
|
#define __IO_PREFIX cia
|
|
#define cia_trivial_rw_bw 2
|
|
#define cia_trivial_rw_lq 1
|
|
#define cia_trivial_io_bw 0
|
|
#define cia_trivial_io_lq 0
|
|
#define cia_trivial_iounmap 1
|
|
#include <asm/io_trivial.h>
|
|
|
|
#undef __IO_PREFIX
|
|
#define __IO_PREFIX cia_bwx
|
|
#define cia_bwx_trivial_rw_bw 1
|
|
#define cia_bwx_trivial_rw_lq 1
|
|
#define cia_bwx_trivial_io_bw 1
|
|
#define cia_bwx_trivial_io_lq 1
|
|
#define cia_bwx_trivial_iounmap 1
|
|
#include <asm/io_trivial.h>
|
|
|
|
#undef __IO_PREFIX
|
|
#ifdef CONFIG_ALPHA_PYXIS
|
|
#define __IO_PREFIX cia_bwx
|
|
#else
|
|
#define __IO_PREFIX cia
|
|
#endif
|
|
|
|
#ifdef __IO_EXTERN_INLINE
|
|
#undef __EXTERN_INLINE
|
|
#undef __IO_EXTERN_INLINE
|
|
#endif
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif /* __ALPHA_CIA__H__ */
|